- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16261 > DS26522DK (Maxim Integrated Products)KIT DESIGN FOR DS26522 PDF資料下載
參數(shù)資料
| 型號： | DS26522DK |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 200/258頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DESIGN FOR DS26522 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 設(shè)計資源： | DS26522DK Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 電信，調(diào)幀器和線路接口裝置（LIU） |
| 已用 IC / 零件： | DS26522 |
| 已供物品： | 板，CD |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁當(dāng)前第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁
DS26522 Dual T1/E1/J1 Transceiver
46 of 258
8.9.4.3 Receive-Signaling Operation
There are two methods to access receive-signaling data and provide transmit-signaling data: processor based (i.e.,
software based) or hardware based. Processor based refers to access through the transmit- and receive-signaling
registers, RS1:RS16. Hardware based refers to the RSIG pin. Both methods can be used simultaneously.
8.9.4.3.1 Processor-Based Signaling
Signaling information is sampled from the receive data stream and copied into the receive-signaling registers,
RS1:RS16. The signaling information in these registers is always updated on multiframe boundaries. This function
is always enabled.
8.9.4.3.2 Change of State
To avoid constant monitoring of the receive-signaling registers, the DS26522 can be programmed to alert the host
when any specific channel or channels undergo a change of their signaling state. RSCSE1:RSCSE4 are used to
select which channels can cause a change-of-state indication. The change of state is indicated in Latched Status
Register 4 (RLS4.3). If signaling integration is enabled, the new signaling state must be constant for three
multiframes before a change-of-state indication is indicated. The user can enable the
INTB pin to toggle low upon
detection of a change in signaling by setting the interrupt mask bit RIM4.3. The signaling integration mode is global
and cannot be enabled on a channel-by-channel basis.
The user can identity which channels have undergone a signaling change of state by reading the receive-signaling
status (RSS1:RSS4) registers. The information from these registers tells the user which RSx register to read for the
new signaling data. All changes are indicated in the RSS1:RSS4 registers regardless of the RSCSE1:RSCSE4
registers.
8.9.4.3.3 Hardware-Based Receive Signaling
In hardware-based signaling, the signaling data can be obtained from the RSER pin or the RSIG pin. RSIG is a
signaling PCM stream output on a channel-by-channel basis from the signaling buffer. The T1 robbed bit or E1
TS16 signaling data is still present in the original data stream at RSER. The signaling buffer provides signaling data
to the RSIG pin and also allows signaling data to be reinserted into the original data stream in a different alignment
that is determined by a multiframe signal from the RSYNC pin. In this mode, the receive elastic store can be
enabled or disabled. If the receive elastic store is enabled, the backplane clock (RSYSCLK) can be either
1.544MHz or 2.048MHz. In the ESF framing mode, the ABCD signaling bits are output on RSIG in the lower nibble
of each channel. The RSIG data is updated once a multiframe (3ms for T1 ESF, 1.5ms for T1 D4, 2ms for E1 CAS)
unless a signaling freeze is in effect. In the D4 framing mode, the AB signaling bits are output twice on RSIG in the
lower nibble of each channel. Thus, bits 5 and 6 contain the same data as bits 7 and 8, respectively, in each
channel.
8.9.4.3.4 Receive-Signaling Reinsertion at RSER
In this mode, the user provides a multiframe sync at the RSYNC pin and the signaling data will be reinserted based
on this alignment. In T1 mode, this results in two copies of the signaling data in the RSER data stream. The original
signaling data is based on the Fs/ESF frame positions, and the realigned data is based on the user-supplied
multiframe sync applied at RSYNC. In voice channels, this extra copy of signaling data is of little consequence.
Reinsertion can be avoided in data channels since this feature is activated on a per-channel basis. For reinsertion,
the elastic store must be enabled; for T1, the backplane clock can be either 1.544MHz or 2.048MHz. E1 signaling
information cannot be reinserted into a 1.544MHz backplane.
Signaling-reinsertion mode is enabled on a per-channel basis by setting the receive-signaling reinsertion channel
select bit high in the Receive-Signaling Reinsertion Enable register (RSI1:RSI4). The channels that are to have
signaling reinserted are selected by writing to the RSI1:RSI4 registers. In E1 mode, the user generally selects all
channels or none for reinsertion.
8.9.4.3.5 Force Receive-Signaling All Ones
In T1 mode, the user can, on a per-channel basis, force the robbed-bit signaling bit positions to 1. This is done by
using the T1-mode Receive-Signaling All-Ones Insertion registers (T1RSAOI1:T1RSAOI3). The user sets the
channel select bit in the T1RSAOI1:T1RSAOI3 registers to select the channels that are to have the signaling forced
to one.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EMM08DSEF-S13 | CONN EDGECARD 16POS .156 EXTEND |
| DS26528DK | KIT DESIGN FOR DS26528 |
| ESM12DRTN-S13 | CONN EDGECARD 24POS .156 EXTEND |
| M3TFK-1636J | IDC CABLE - MSD16K/MC16G/MCF16K |
| EMM10DRTI-S13 | CONN EDGECARD 20POS .156 EXTEND |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS26522G | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 2-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS26522G+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 2-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS26522GN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 2-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS26522GN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 2-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS26524 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Quad T1/E1/J1 Transceiver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。