VEE IN- IN+ OUT+ OUT- V
參數(shù)資料
型號: DS30EA101SQE/NOPB
廠商: National Semiconductor
文件頁數(shù): 5/12頁
文件大?。?/td> 0K
描述: IC CABLE EQUALIZER 16LLP
標(biāo)準(zhǔn)包裝: 250
系列: *
1
4
3
2
DS30EA101
(top view)
12
9
10
11
8
5
6
7
13
16
15
14
VEE
IN-
IN+
OUT+
OUT-
VEE
D
N
C
D
N
C
L
O
S
V
C
V
C
EN
DAP = VEE
VEE
V
EE
V
EE
SNLS404A – FEBRUARY 2012 – REVISED APRIL 2013
Connection Diagram
The exposed die attach pad is a negative electrical terminal for this device. It should be connected to the negative
power supply voltage.
Figure 1. 16-Pin WQFN Package
See Package Number RUM0016A
PIN DESCRIPTIONS
Pin
Name
I/O, Type
Description
1
VEE
Ground
Negative power supply (ground).
2
IN+
I, Data
Non-inverting input.
3
IN-
I, Data
Inverting input.
4
VEE
Ground
Negative power supply (ground).
5
DNC
N/A
Do not connect – leave open.
6
DNC
N/A
Do not connect – leave open.
7
VEE
Ground
Negative power supply (ground).
8
VEE
Ground
Negative power supply (ground).
9
VEE
Ground
Negative power supply (ground).
10
OUT-
O, LVDS
Inverting output.
11
OUT+
O, LVDS
Non-inverting output.
12
VEE
Ground
Negative power supply (ground).
13
VCC
Power
Positive power supply (+2.5V).
14
EN
I, LVCMOS
Output enable. LOS may be tied to this pin to inhibit the output when no input signal is
present. This pin has an internal pulldown.
H = Outputs disabled.
L = Outputs enabled.
15
LOS
O, LVCMOS
Loss of signal.
H = No input signal detected.
L = Input signal detected.
16
VCC
Power
Positive power supply (+2.5V).
DAP
VEE
Ground
Connect exposed DAP to negative power supply (ground).
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
Copyright 2012–2013, Texas Instruments Incorporated
Product Folder Links: DS30EA101
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