參數(shù)資料
型號: DS3112D1+
廠商: Maxim Integrated Products
文件頁數(shù): 119/133頁
文件大?。?/td> 0K
描述: IC MUX T3/E3 3.3V 256-PBGA
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 40
控制器類型: 調幀器,多路復用器
接口: 并行/串行
電源電壓: 3.135 V ~ 3.465 V
電流 - 電源: 150mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA
供應商設備封裝: 256-PBGA(27x27)
包裝: 管件
DS3112
86 of 133
Register Description:
Figure 8-1. BERT Status Bit Flow
Alarm Latch
Change in State Detect
RLOS
(BERTEC0
Bit 4)
Internal RLOS
Signal from
BERT
Event Latch
Internal Bit
Error Detected
Signal from
BERT
Event Latch
Internal Counter
Overflow
Signal from
BERT
OR
BED
(BERTEC0
Bit 3)
BECO or BBCO
(BERTEC0
Bits 1 & 2)
Mask
BERT
(IMSR Bit 2)
INT*
Hardware
Signal
BERT
Status Bit
(MSR Bit 2)
Mask
IESYNC (BERTC0 Bit 15)
Mask
IEBED (BERTC0 Bit 14)
IEOF (BERTC0 Bit 13)
Event Latch
NOTE: ALL EVENT AND ALARM LATCHES ABOVE ARE CLEARED WHEN THE BERTEC0 REGISTER IS READ.
Register Name:
BERTEC1
BERT 24-Bit Error Counter (upper)
Register Address:
7Eh
Bit #
7
6
5
4
3
2
1
0
Name
BEC15
BEC14
BEC13
BEC12
BEC11
BEC10
BEC9
BEC8
Default
0
Bit #
15
14
13
12
11
10
9
8
Name
BEC23
BEC22
BEC21
BEC20
BEC19
BEC18
BEC17
BEC16
Default
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15: BERT 24-Bit Error Counter (BEC8 to BEC23). Upper two bytes of the 24-bit counter. This 24-bit
counter will increment for each data bit received in error. This counter is not disabled when the receive BERT loses
synchronization. This counter can be cleared by toggling the LC control bit in BERTBC0. This counter saturates
and will not rollover. Upon saturation, the BECO status bit in the BERTEC0 register will be set. This error counter
starts counting when the BERT goes into receive synchronization (RLOS = 0 or SYNC = 1) and it will not stop
counting when the BERT loses synchronization. It is recommended that the host toggle the LC bit in BERTC0
register once the BERT has synchronized and then toggle the LC bit again when the error checking period is
complete. If the device loses synchronization during this period, then the counting results are suspect.
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