參數(shù)資料
型號: DS3131
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Telecom IC:Other
英文描述: SPECIALTY TELECOM CIRCUIT, PBGA256
封裝: 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù): 126/174頁
文件大?。?/td> 1261K
代理商: DS3131
DS3131
55 of 174
Register Name:
BERTC1
Register Description:
BERT Control Register 1
Register Address:
0504h
Bit #
7
6
5
4
3
2
1
0
Name
EIB2
EIB1
EIB0
SBE
reserved
TC
Default
0
Bit #
15
14
13
12
11
10
9
8
Name
Alternating Word Count
Default
0
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Transmit Pattern Load (TC). A low-to-high transition loads the pattern generator with repetitive or
pseudorandom pattern that is to be generated. This bit should be toggled from low to high whenever the host
wishes to load a new pattern. Must be cleared and set again for subsequent loads.
Bit 4/Single Bit-Error Insert (SBE). A low-to-high transition creates a single bit error. Must be cleared and set
again for a subsequent bit error to be inserted.
Bit 5/Error Insert Bit 0 (EIB0); Bit 6/Error Insert Bit 1 (EIB1); Bit 7/Error Insert Bit 2 (EIB2).
Automatically inserts bit errors at the prescribed rate into the generated data pattern. Useful for verifying error
detection operation.
EIB2
EIB1
EIB0
Error Rate Inserted
0
No errors automatically inserted
0
1
10E-1
0
1
0
10E-2
0
1
10E-3
1
0
10E-4
1
0
1
10E-5
1
0
10E-6
1
10E-7
Bits 8 to 15/Alternating Word Count Rate. When the BERT is programmed in the alternating word mode, the
words repeat for the count loaded into this register, then flip to the other word and again repeat for the number of
times loaded into this register. The valid count range is from 05h to FFh.
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