參數(shù)資料
型號： DS3154N#
廠商： Maxim Integrated Products
文件頁數(shù)： 31/61頁
文件大?。?/td> 0K
描述： IC LIU DS3/E3/STS-1 144-CSBGA
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 160
類型： 線路接口裝置（LIU）
驅(qū)動器/接收器數(shù)： 4/4
規(guī)程： IEEE 1149.1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 144-BGA，CSPBGA
供應商設備封裝： 144-TECSBGA（13x13）
包裝： 管件
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
37 of 61
13.
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Lead with Respect to VSS (except VDD)
-0.3V to +5.5V
Supply Voltage Range (VDD) with Respect to VSS
-0.3V to +3.63V
Ambient Operating Temperature Range
-40°C to +85°C
Junction Operating Temperature Range
-40°C to +125°C
Storage Temperature Range
-55°C to +125°C
Soldering Temperature
See IPC/JEDEC J-STD-020A Specification
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Ambient operating
temperature range when device is mounted on a four-layer JEDEC test board with no airflow.
Note: The typical values listed in Tables 13-A through 13-I are not production tested.
Table 13-A. Recommended DC Operating Conditions
(TA = -40°C to +85°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Logic 1
VIH
2.0
5.5
V
Logic 0
VIL
-0.3
+0.8
V
Supply Voltage
VDD
3.135
3.3
3.465
V
Table 13-B. DC Characteristics
(VDD = 3.3V ±5%, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DS3151
75
100
DS3152
150
200
DS3153
225
300
Supply Current (Note 1)
IDD
DS3154
300
400
mA
DS3151
65
80
DS3152
120
150
DS3153
180
225
Supply Current, Transmitters Tri-Stated
(All
TTSn Low) (Note 2)
IDDTTS
DS3154
240
300
mA
Power-Down Current (All TPD, RPD
Control Bits High)
IDDPD
DS315x (Note 2)
55
70
mA
Lead Capacitance
CIO
7
pF
Input Leakage
IIL
(Note 3)
-50
+10
μA
Output Leakage (when High-Z)
ILO
(Note 3)
-10
+10
μA
Output Voltage (IO = -4.0mA)
VOH
2.4
VDD
V
Output Voltage (IO = +4.0mA)
VOL
0
0.4
V
Note 1: TCLKn = STMCLK = 51.84MHz; TXPn/TXNn driving all ones into 75
Ω resistive loads; analog loopback enabled; all other inputs at V
DD
or grounded; all other outputs open.
Note 2: TCLKn = STMCLK = 51.84MHz; other inputs at VDD or grounded; digital outputs left open circuited.
Note 3: 0V < VIN < VDD.
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