參數(shù)資料
型號: DS3253N+
廠商: Maxim Integrated Products
文件頁數(shù): 6/71頁
文件大?。?/td> 0K
描述: IC LIU DS3/E3/STS-1 144-CSBGA
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 160
類型: 線路接口裝置(LIU)
驅動器/接收器數(shù): 3/3
規(guī)程: IEEE 1149.1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 144-BGA,CSPBGA
供應商設備封裝: 144-TECSBGA(13x13)
包裝: 托盤
DS3251/DS3252/DS3253/DS3254
14 of 71
Table 6-G. Transmitter Data Select Options
TDSA
TDSB
E3M
STS
Tx
MODE
TRANSMIT DATA SELECTED
0
X
Any
Normal data as input at TPOS and TNEG
0
1
0
DS3
0
1
0
E3
0
1
STS-1
Unframed all ones
0
1
0
1
DS3
DS3 AIS per ANSI T1.107 (Figure 9-2)
1
0
X
Any
Unframed 100100… pattern
1
0
E3
2
23 - 1 PRBS pattern per ITU O.151
1
0
X
DS3
1
STS-1
2
15 - 1 PRBS pattern per ITU O.151
Note 1:
This coding of the TDSA, TDSB, E3M, and STS bits allows AIS generation to be enabled by
holding TDSA = 0 and changing TDSB from 0 to 1. The type of DS3 AIS signal is selected by the
STS bit with E3M = 0.
Note 2:
If E3M and/or STS are changed when {TDSA,TDSB}
≠ 00, TDSA and TDSB must both be cleared
to 0. After they are cleared, TDSA and TDSB can be configured to transmit a pattern in the new
operating mode.
Table 6-H. Receiver PRBS Pattern Select Options
E3M
STS
Rx
MODE
RECEIVER PRBS PATTERN
SELECTED
1
0
E3
2
23 - 1 PRBS pattern per ITU O.151
0
X
DS3
1
STS-1
2
15 - 1 PRBS pattern per ITU O.151
Table 6-I. Hardware Mode Jitter Attenuator Configuration
TJA
RJA
JITTER ATTENUATOR CONFIGURATION
0
Disabled
0
1
Receive path, 16-bit buffer depth
1
0
Transmit path, 16-bit buffer depth
1
Transmit path, 32-bit buffer depth
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