參數(shù)資料
型號: DS3254+
廠商: Maxim Integrated Products
文件頁數(shù): 7/71頁
文件大?。?/td> 0K
描述: IC LIU DS3/E3/STS-1 144-CSBGA
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 160
類型: 線路接口裝置(LIU)
驅動器/接收器數(shù): 4/4
規(guī)程: IEEE 1149.1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 144-BGA,CSPBGA
供應商設備封裝: 144-TECSBGA(13x13)
包裝: 托盤
DS3251/DS3252/DS3253/DS3254
15 of 71
7. REGISTER DESCRIPTIONS
When the DS325x is configured in either of the two CPU bus modes (HW = 0), the registers shown in Table 7-A
are accessible through the CPU bus interfaces. All registers for the LIU ports are forced to their default values
during an internal power-on reset or when the
RST pin is driven low. Setting an LIU’s RST bit high forces all
registers for that LIU to their default values. All register bits marked “—” must be written 0 and ignored when read.
The TEST registers must be left at their reset value of 00h for normal operation.
On the DS3253, only registers for LIUs 1, 2, and 3 are available. Writes into LIU 4 address space are ignored.
Reads from LIU 4 address space return all zeros. On the DS3252, address line A5 is not present, limiting the
address space to the LIU 1 and LIU 2 registers. On the DS3251, address lines A5 and A4 are not present, limiting
the address space to the LIU 1 registers.
Table 7-A. Register Map
ADDRESS
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LIU 1
00h
E3M
STS
LLB
RLB
TDSA
TDSB
RST
01h
JAL[1]
TBIN
TCINV
TJA
TPD
TTS
TLBO
JAL[0]
02h
ITU
RBIN
RCINV
RJA
RPD
RTS
RMON
RCVUD
03h
TDM
PRBS
RLOL
RLOS
04h
JAFL
JAEL
TDML
PRBSL
PBERL
RCVL
RLOLL
RLOSL
05h
JAFIE
JAEIE
TDMIE
PRBSIE
PBERIE
RCVIE
RLOLIE
RLOSIE
06h
RCV[7]
RCV[6]
RCV[5]
RCV[4]
RCV[3]
RCV[2]
RCV[1]
RCV[0]
07h
RCV[15]
RCV[14]
RCV[13]
RCV[12]
RCV[11]
RCV[10]
RCV[9]
RCV[8]
08h
T3MOE
E3MOE
STMOE
AMCSEL[1] AMCSEL[0]
AMCEN
09h–0Fh
Test Registers
LIU 2
10h
E3M
STS
LLB
RLB
TDSA
TDSB
RST
11h
JAL[1]
TBIN
TCINV
TJA
TPD
TTS
TLBO
JAL[0]
12h
ITU
RBIN
RCINV
RJA
RPD
RTS
RMON
RCVUD
13h
TDM
PRBS
RLOL
RLOS
14h
JAFL
JAEL
TDML
PRBSL
PBERL
RCVL
RLOLL
RLOSL
15h
JAFIE
JAEIE
TDMIE
PRBSIE
PBERIE
RCVIE
RLOLIE
RLOSIE
16h
RCV[7]
RCV[6]
RCV[5]
RCV[4]
RCV[3]
RCV[2]
RCV[1]
RCV[0]
17h
RCV[15]
RCV[14]
RCV[13]
RCV[12]
RCV[11]
RCV[10]
RCV[9]
RCV[8]
18h
unused
19h–1Fh
Test Registers
LIU 3
20h
E3M
STS
LLB
RLB
TDSA
TDSB
RST
21h
JAL[1]
TBIN
TCINV
TJA
TPD
TTS
TLBO
JAL[0]
22h
ITU
RBIN
RCINV
RJA
RPD
RTS
RMON
RCVUD
23h
TDM
PRBS
RLOL
RLOS
24h
JAFL
JAEL
TDML
PRBSL
PBERL
RCVL
RLOLL
RLOSL
25h
JAFIE
JAEIE
TDMIE
PRBSIE
PBERIE
RCVIE
RLOLIE
RLOSIE
26h
RCV[7]
RCV[6]
RCV[5]
RCV[4]
RCV[3]
RCV[2]
RCV[1]
RCV[0]
27h
RCV[15]
RCV[14]
RCV[13]
RCV[12]
RCV[11]
RCV[10]
RCV[9]
RCV[8]
28h
unused
29h–2Fh
Test Registers
LIU 4
30h
E3M
STS
LLB
RLB
TDSA
TDSB
RST
31h
JAL[1]
TBIN
TCINV
TJA
TPD
TTS
TLBO
JAL[0]
32h
ITU
RBIN
RCINV
RJA
RPD
RTS
RMON
RCVUD
33h
TDM
PRBS
RLOL
RLOS
34h
JAFL
JAEL
TDML
PRBSL
PBERL
RCVL
RLOLL
RLOSL
35h
JAFIE
JAEIE
TDMIE
PRBSIE
PBERIE
RCVIE
RLOLIE
RLOSIE
36h
RCV[7]
RCV[6]
RCV[5]
RCV[4]
RCV[3]
RCV[2]
RCV[1]
RCV[0]
37h
RCV[15]
RCV[14]
RCV[13]
RCV[12]
RCV[11]
RCV[10]
RCV[9]
RCV[8]
38h
unused
39h–3Fh
Test Registers
Note 1: Underlined bits are read-only; all other bits are read-write.
Note 2: The registers are named REGn, where n = the LIU number (1, 2, 3, or 4). The register names are hyperlinks to the register descriptions.
Note 3: The bit names are the same for each LIU register set.
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