- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1916 > DS33R11+CJ2 (Maxim Integrated Products)IC ETH TXRX T1/E1/J1 256-BGA PDF資料下載
參數(shù)資料
| 型號(hào)： | DS33R11+CJ2 |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 308/344頁 |
| 文件大小： | 0K |
| 描述： | IC ETH TXRX T1/E1/J1 256-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 收發(fā)器 |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 1.8V, 3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BBGA |
| 供應(yīng)商設(shè)備封裝： | 256-BGA（27x27） |
| 包裝： | 托盤 |
| 其它名稱： | 90-33R11+C01 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁第262頁第263頁第264頁第265頁第266頁第267頁第268頁第269頁第270頁第271頁第272頁第273頁第274頁第275頁第276頁第277頁第278頁第279頁第280頁第281頁第282頁第283頁第284頁第285頁第286頁第287頁第288頁第289頁第290頁第291頁第292頁第293頁第294頁第295頁第296頁第297頁第298頁第299頁第300頁第301頁第302頁第303頁第304頁第305頁第306頁第307頁當(dāng)前第308頁第309頁第310頁第311頁第312頁第313頁第314頁第315頁第316頁第317頁第318頁第319頁第320頁第321頁第322頁第323頁第324頁第325頁第326頁第327頁第328頁第329頁第330頁第331頁第332頁第333頁第334頁第335頁第336頁第337頁第338頁第339頁第340頁第341頁第342頁第343頁第344頁
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
66 of 344
9.18 Receive Packet Processor
The Receive Packet Processor accepts data from the Receive Serial Interface performs packet descrambling,
packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet size checking, FCS error
monitoring, FCS byte extraction, and bit reordering. The data coming from the Receive Serial Interface is a serial
data stream. Packet processing can be disabled (clear channel enable). Disabling packet processing disables
packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet size checking, FCS error
monitoring, and FCS byte extraction. Only packet descrambling and bit reordering are not disabled.
The packet descrambler is a self-synchronous x
43 + 1 descrambler that descrambles the entire packet data stream.
Packet descrambling is programmable. The descrambler runs continuously, and is never reset. The descrambling
is performed one bit at a time. Packet descrambling is programmable. If packet processing is disabled, the serial
data stream is demultiplexed in to an 8-bit data stream before being passed on.
If packet processing is disabled, a packet boundary is arbitrarily chosen and the data is divided into "packets" of
programmable size (dependent on maximum packet size setting). These packets are then passed on to bit
reordering with packet start and packet end indications. Data then bypasses packet delineation, inter-frame fill
filtering, packet abort detection, destuffing, packet size checking, FCS error monitoring, and FCS byte extraction.
Packet delineation determines the packet boundary by identifying a packet start or end flag. Each time slot is
checked for a flag sequence (7Eh). Once a flag is found, it is identified as a start/end flag and the packet boundary
is set. The flag check is performed one bit at a time. If packet processing is disabled, packet delineation is not
performed.
Inter-frame fill filtering removes the inter-frame fill between packets. When a packet end flag is detected, all data is
discarded until a packet start flag is detected. The inter-frame fill can be flags or all '1's. The number of '1's
between flags does not need to be an integer number of bytes, and if at least 7 '1's are detected in the first 16 bits
after a flag, all data after the flag is discarded until a start flag is detected. There may be only one flag between
packets. When the inter-frame fill is flags, the flags may have a shared zero (011111101111110). If there is less
than 16 bits between two flags, the data is discarded. If packet processing is disabled, inter-frame fill filtering is not
performed.
Packet abort detection searches for a packet abort sequence. Between a packet start flag and a packet end flag, if
an abort sequence is detected, the packet is marked with an abort indication, the aborted packet count is
incremented, and all subsequent data is discarded until a packet start flag is detected. The abort sequence is
seven consecutive ones. If packet processing is disabled, packet abort detection is not performed.
Destuffing removes the extra data inserted to prevent data from mimicking a flag or an abort sequence. A start flag
is detected, a packet start is set, the flag is discarded, destuffing is performed until an end flag is detected, a
packet end is set, and the flag is discarded. In bit synchronous mode, bit destuffing is performed. Bit destuffing
consists of discarding any '0' that directly follows five contiguous '1's. After destuffing is completed, the serial bit
stream is demultiplexed into an 8-bit parallel data stream and passed on with packet start, packet end, and packet
abort indications. If there is less than eight bits in the last byte, an invalid packet flag is raised, the packet is tagged
with an abort indication, and the packet size violation count is incremented. If packet processing is disabled,
destuffing is not performed.
Packet size checking checks each packet for a programmable maximum and programmable minimum size. As the
packet data comes in, the total number of bytes is counted. If the packet length is below the minimum size limit, the
packet is marked with an aborted indication, and the packet size violation count is incremented. If the packet length
is above the maximum size limit, the packet is marked with an aborted indication, the packet size violation count is
incremented, and all packet data is discarded until a packet start is received. The minimum and maximum lengths
include the FCS bytes, and are determined after destuffing has occurred. If packet processing is disabled, packet
size checking is not performed.
FCS error monitoring checks the FCS and aborts errored packets. If an FCS error is detected, the FCS errored
packet count is incremented and the packet is marked with an aborted indication. If an FCS error is not detected,
the receive packet count is incremented. The FCS type (16-bit or 32-bit) is programmable. If FCS processing or
packet processing is disabled, FCS error monitoring is not performed.
FCS byte extraction discards the FCS bytes. If FCS extraction is enabled, the FCS bytes are extracted from the
packet and discarded. If FCS extraction is disabled, the FCS bytes are stored in the receive FIFO with the packet.
If FCS processing or packet processing is disabled, FCS byte extraction is not performed.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS33R41+ | IC TXRX ETHERNET MAP 400-BGA |
| DS33W11DK+ | IC MAPPING ETHERNET 256-CSBGA |
| DS33Z11+UNUSED | IC ETHERNET MAPPER 169-CSBGA |
| DS33Z44+ | IC MAPPER ETHERNET 256CSBGA |
| DS33ZH11+ | IC MAPPER ETHERNET 100CSBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS33R11DK | 功能描述:以太網(wǎng)開發(fā)工具 DS33R11 Dev Kit RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| DS33R41 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Inv-Mult Enet Mapper w/Quad T1/E1/J1 Trx RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS33R41+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Inv-Mult Enet Mapper w/Quad T1/E1/J1 Trx RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS33W11+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Ethernet Over PDH Mapping Devices RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS33W11DK+ | 功能描述:以太網(wǎng)開發(fā)工具 1/1 E-Net - PDH Design Kit RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。