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參數(shù)資料
| 型號(hào)： | DS3502U+T&R/C |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 9/11頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL NV 128TAP 10-USOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 接片： | 128 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 ±4 ppm/°C |
| 存儲(chǔ)器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-µMAX |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 90-3502T+C00 |
DS3502
High-Voltage, NV, I2C POT
_______________________________________________________________________________________
7
Slave Address Byte and Address Pins
The slave address byte consists of a 7-bit slave
address plus a R/W bit (see Figure 1). The DS3502’s
slave address is determined by the state of the A0 and
A1 address pins. These pins allow up to four devices to
reside on the same I2C bus. Address pins tied to GND
result in a 0 in the corresponding bit position in the
slave address. Conversely, address pins tied to VCC
result in a 1 in the corresponding bit positions. For
example, the DS3502’s slave address byte is 50h when
A0 and A1 pins are grounded. I2C communication is
described in detail in the
I2C Serial Interface
Description section.
I2C Serial Interface Description
I2C Definitions
The following terminology is commonly used to describe
I2C data transfers. (See Figure 2 and the
I2C AC Electrical
Characteristics table for additional information.)
Master device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses and START and STOP conditions.
Slave devices: Slave devices send and receive data at
the master’s request.
Bus idle or not busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states.
START condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition.
STOP condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition.
Repeated START condition: The master can use a
repeated START condition at the end of one data trans-
fer to indicate that it will immediately initiate a new data
transfer following the current one. Repeated STARTS are
commonly used during read operations to identify a spe-
cific memory address to begin a data transfer. A repeat-
ed START condition is issued identically to a normal
START condition.
Bit write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements. Data is shifted into the
device during the rising edge of the SCL.
Bit read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time before the next rising edge of SCL during a
bit read. The device shifts out each bit of data on SDA
at the falling edge of the previous SCL pulse and the
0
1
0
R/W
A0
A1
0
MSB
LSB
SLAVE ADDRESS*
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1.
Figure 1. DS3502 Slave Address Byte
SDA
SCL
tHD:STA
tLOW
tHIGH
tR
tF
tBUF
tHD:DAT
tSU:DAT
REPEATED
START
tSU:STA
tHD:STA
tSU:STO
tSP
STOP
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
START
Figure 2. I2C Timing Diagram
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