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參數(shù)資料
| 型號： | DS3502U+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL NV 128TAP 10-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 3,000 |
| 接片： | 128 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標準值 ±4 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-µMAX |
| 包裝： | 帶卷 (TR) |
DS3502
High-Voltage, NV, I2C POT
4
_______________________________________________________________________________________
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.5V to +5.5V)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TA = +70°C
50,000
EEPROM Write Cycles
TA = +25°C
200,000
Writes
Note 1:
All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are negative.
Note 2:
ICC is specified with the following conditions: SCL = 400kHz, SDA pulled up, and RL, RW, RH floating.
Note 3:
ISTBY is specified with SDA = SCL = VCC = 5.5V and resistor pins floating.
Note 4:
This is the minimum VCC voltage that causes NV memory to be recalled.
Note 5:
This is the time from VCC > VPOR until initial memory recall is complete.
Note 6:
Integral nonlinearity is the deviation of a measured resistor setting value from the expected values at each particular resis-
tor setting. Expected value is calculated by connecting a straight line from the measured minimum setting to the mea-
sured maximum setting. INL = [V(RW)i - (V(RW)0]/LSB(ideal) - i, for i = 0...127.
Note 7:
Differential nonlinearity is the deviation of the step-size change between two LSB settings from the expected step size.
The expected LSB step size is the slope of the straight line from measured minimum position to measured maximum posi-
tion. DNL = [V(RW)i+1 - (V(RW)i]/LSB(ideal) - 1, for i = 0...126.
Note 8:
ZS error = code 0 wiper voltage divided by one LSB (ideal).
Note 9:
FS error = (code 127 wiper voltage - V+) divided by one LSB (ideal).
Note 10: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C standard
mode timing.
Note 11: CB—total capacitance of one bus line in picofarads.
Note 12: EEPROM write time begins after a STOP condition occurs.
Note 13: Pulses narrower than max are suppressed.
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