
Test Circuits
(Continued)
TL/F/5816–10
Each input is tested separately.
FIGURE 2. I
IH
TL/F/5816–11
Note A:
Each input is tested separately.
Note B:
When testing DS1633 and DS1634 input not under test is grounded.
For all other circuits it is at V
CC
.
FIGURE 3. I
IL
TL/F/5816–12
Both gates are tested simultaneously.
FIGURE 4. I
CC
for AND and NAND Circuits
Schematic Diagram
(Equivalent Circuit)
TL/F/5816–15
4