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參數(shù)資料
| 型號(hào)： | DS38C86AVB |
| 元件分類： | 通用總線功能 |
| 英文描述： | 9-Bit Bus Transceiver |
| 中文描述： | 9位總線收發(fā)器 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 155K |
| 代理商： | DS38C86AVB |
AC Electrical Characteristics
(Note 6) (Continued)
T
= 0C to +70C, V
= 5V
±
10%
DRIVER
(REN = 0V for all conditions)
Symbol
RECEIVER
t
PLZ
T/R to An
t
PZL
t
PHZ
t
PZH
t
SKEW
LE to An, Same Package
Bn to An, Same Package
RECEIVER TIMING REQUIREMENTS
(Figure 7)
t
S
Bn to LE (Set-Up Time)
t
H
LE to Bn (Hold Time)
t
PW
LE Pulse Width
PARAMETERS NOT TESTED
C
OUTPUT
Capacitance at Bn
t
NR
Noise Rejection
Parameter
Conditions
Min
Typ
Max
Units
Disable Time
Enable Time
Disable Time
Enable Time
LE = V
CC
, Bn = 2.1V, CD = 0V
(Figures 10, 11)
LE = V
CC
, Bn = 1.1 CD = 0V
(Figures 8, 9)
(Note 7)
(Note 7)
3.0
3.0
3.0
3.0
6.0
5.0
7.3
5.5
0.6
0.7
9.0
9.0
12.0
12.0
2.5
2.5
ns
ns
ns
ns
ns
ns
CD = 0V, T/R = 0V
3
1
5
ns
ns
ns
(Note 9)
(Note 10)
3
1
pF
ns
Note 1:
“Absolute Maximum Ratings” are these beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should
be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
Note 2:
All input and/or output pins shall not exceed V
+0.5V and shall not exceed the absolute maximum rating at any time, including power-up and power-down.
This prevents the ESD structure from being damaged due to excessive currents flowing from the input and/or output pins to QV
and V
. There is a diode between
each input and/or output to V
which is forward biased when incorrent sequencing is applied. LI and Bn pins do not have power sequencing requirements with re-
spect to V
CC
and QV
CC
. Furthermore, the difference between V
CC
and QV
CC
should never be greater than 0.5V at any time including power-up.
Note 3:
All currents into device pins are positive; all currents out of device pins are negative.All voltages are referenced to device ground unless otherwise specified.
All typical values are specified under these conditions: V
CC
= 5V and T
A
= 25C, unless otherwise stated.
Note 4:
Only one output should be shorted at a time, and duration of the short should not exceed one second.
Note 5:
Referenced to appropriate signal ground. Do not exceed maximum power dissipation of package.
Note 6:
Input waveforms shall have a rise and fall time of 3 ns.
Note 7:
t
SKEW
is the absolute value defined as the difference seen in propagation delay between drivers (receivers) in the same package with identical load con-
ditions.
Note 8:
This parameter is tested using TDR techniques described in 1194.0 BTL Backplane Design Guide.
Note 9:
This parameter is tested during device characterization. The measurements revealed that the part will reject 1 ns pulse width.
Note 10:
Futurebus+ transceivers are required to limit bus signal rise and fall times to no faster then 0.5 V/ns, measured between 1.3V to 1.8V (approximately 20%
to 80% of the nominal voltage swing). The rise and fall times are measured with a transceiver loading equivalent to 12.5
ties to +2.1 V
DC
.
Note 11:
Capacitance includes jig and probe capacitance.
Note 12:
All pins meet 2 kV typical, one device failure observed between An and QV
CC
in ESD rel sample.
Pin Description
Pin Name
No. of
Pins
9
1
9
9
Input/Output
Description
A0–A8
ACLK
B0–B8
I/O
I
I/O
NA
TTL driver input and TRI-STATE receiver output
Clock input for latch mode
BTL receiver input and driver output
Driver output ground reduces ground bounce due to high current switching of
driver outputs. (Note 11)
Chip disable
Ground reference for switching circuits (Note 11)
Latch enable
Power supply for live insertion. Boards that require live insertion should connect
LI to the live insertion pin on the connector. (Note 12)
No connect
Ground reference for receiver input bandgap reference and non-switching
circuits (Note 12)
Power supply for bandgap reference and non-switching circuits (Note 12)
Register bypass enable
B0 GND–B8 GND
CD
GND
LE
LI
1
2
1
1
I
NA
I
NA
NC
9
1
NA
NA
QGND
QV
CC
RBYP
1
1
NA
I
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