參數(shù)資料
型號(hào)： DS3908N+T&R
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 3/11頁(yè)
文件大?。?/td> 0K
描述： IC POT DUAL DIGITAL 14-TDFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
接片： 64
電阻（歐姆）： 100k
電路數(shù)： 2
溫度系數(shù)： 標(biāo)準(zhǔn)值 50 ppm/°C
存儲(chǔ)器類型： 非易失
接口： I²C（設(shè)備位址）
電源電壓： 3 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 14-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 14-TDFN-EP（3x3）
包裝： 帶卷 (TR)
DS3908
Dual, 64-Position Nonvolatile Digital
Potentiometer with Buffered Outputs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
2006 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
Heaney
Total Error
The total error in a reading from the DS3908 can be
calculated using the following formula:
PotVoltage = (PotCode / 63) x (VH – VL) + VL
ErrorPOT = (INLERR / 63) x (VH – VL)
ErrorOFFSET = Gain x VOFF
ErrorGAIN = PotVoltage x GainERR
Total Output Error = ErrorPOT + ErrorOFFSET + ErrorGAIN
where:
PotCode = Potentiometer Setting (dec)
GainERR = Amplifier Gain Deviation from Desired (V/V)
VOFF = PGA Input Voltage Offset Voltage (V)
INLERR = Potentiometer Integral Non-Linearity (LSB)
For example, the worst-case error for VH = 2V, VL = 0.5V,
PGA Gain = 2V/V, PotCode = 31d (1Fh), is given by:
PotVoltage = 31 / 63 x (2.0V - 0.5V) + 0.5V = 1.238V
ErrorPOT = (0.6 / 63) x (2.0V - 0.5V) = 0.014V
ErrorOFFSET = 2.0V/V x 9mV = 0.018V
ErrorGAIN = PotVoltage x GainERR = 0.0929V
Total Output Error = ErrorPOT + ErrorOFFSET + ErrorGAIN
= 0.014V + 0.018V + 0.0929V = 0.125V
Package Information
For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.
Chip Topology
TRANSISTOR COUNT: 9950
SLAVE
ADDRESS*
START
1
0
1
0
A2
A1
A0
R/W
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
MSB
LSB
MSB
LSB
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
READ/
WRITE
REGISTER/MEMORY ADDRESS
b7
b6
b5
b4
b3
b2
b1
b0
DATA
STOP
SINGLE BYTE
NONVOLATILE WRITE
-WRITE POTENTIOMETER 1
TO 00h
SINGLE BYTE
VOLATILE WRITE
-WRITE POTENTIOMETER 1
TO 00h
START
STOP
1 0100000
11111 001
A0h
F9h
REPEATED
START
1 0100000
11111 001
A0h
F9h
STOP
POT 0
DATA
EXAMPLE I2C TRANSACTIONS (WHEN A0, A1, AND A2 ARE CONNECTED TO GND)
TYPICAL I2C WRITE TRANSACTION
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1, AND A2.
00 000 000
00000000
SINGLE BYTE READ
-READ POTENTIOMETER 0
A)
B)
START
STOP
101000 00
111 1 1 000
A0h
F8h
A1h
1010 0001
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
MASTER
NACK
REPEATED
START
Figure 3. I2C Communication Examples
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