DS4402/DS4404
Two/Four-Channel, I2C Adjustable Current DAC
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3
Note 1: All voltages with respect to ground. Currents entering the IC are specified positive, and currents exiting the IC are negative.
Note 2: Supply current specified with all outputs set to zero current setting with all inputs (except A1 and A0, which can be open) driven
to well-defined logic levels. SDA and SCL are connected to VCC. Excludes current through RFS resistors (IRFS). Total current
including IRFS is ICC + (2 x IRFS).
Note 3: The output-voltage full-scale current ranges must be satisfied to ensure the device meets its accuracy and linearity specifications.
Note 4: Temperature drift excludes drift caused by external resistor.
Note 5: Differential linearity is defined as the difference between the expected incremental current increase with respect to position
and the actual increase. The expected incremental increase is the full-scale range divided by 31.
Note 6: Integral linearity is defined as the difference between the expected value as a function of the setting and the actual value.
The expected value is a straight line between the zero and the full-scale values proportional to the setting.
Note 7: Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard-mode timing.
Note 8: CB—total capacitance of one bus line in pF.
OUTPUT CURRENT CHARACTERISTICS (continued)
(VCC = +2.7V to +5.5V, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output-Current Power-Supply
Rejection Ratio
DC
0.33
%/V
Output Leakage Current at Zero
Current Setting
IZERO
-1
+1
μA
Output-Current Differential
Linearity
DNL
(Note 5)
0.5
LSB
Output-Current Integral Linearity
INL
(Note 6)
1
LSB
I2C AC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
fSCL
(Note 7)
0
400
kHz
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
s
Hold Time (Repeated) START
Condition
tHD:STA
0.6
s
Low Period of SCL
tLOW
1.3
s
High Period of SCL
tHIGH
0.6
s
Data Hold Time
tDH:DAT
0
0.9
s
Data Setup Time
tSU:DAT
100
ns
START Setup Time
tSU:STA
0.6
s
SDA and SCL Rise Time
tR
(Note 8)
20 +
0.1CB
300
ns
SDA and SCL Fall Time
tF
(Note 8)
20 +
0.1CB
300
ns
STOP Setup Time
tSU:STO
0.6
s
SDA and SCL Capacitive Loading
CB
(Note 8)
400
pF