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參數(shù)資料
| 型號： | DS4426T+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC I2C-MARGINING 4CH 28-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 212 |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | I²C |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-TQFN-EP（4x4） |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁面： | 1421 (CN2011-ZH PDF) |
I2C Serial Interface Description
I2C Definitions
The following terminology is commonly used to
describe I2C data transfers:
I2C Slave Address: The slave address of the
DS4426 is determined by the state of the A0 and A1
pins (see Table 1).
Master Device: The master device controls the slave
devices on the bus. The master device generates
SCL clock pulses and START and STOP conditions.
Slave Devices: Slave devices send and receive
data at the master’s request.
Bus Idle or Not Busy: Time between STOP and
START conditions when both SDA and SCL are inac-
tive and in their logic-high states. When the bus is
idle it often initiates a low-power mode for slave
devices.
START Condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low while SCL
remains high generates a START condition. See
Figure 3 for applicable timing.
STOP Condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL
remains high generates a STOP condition. See
Figure 3 for applicable timing.
Repeated START Condition: The master can use a
repeated START condition at the end of one data
transfer to indicate that it will immediately initiate a
new data transfer following the current one.
operations to identify a specific memory address to
begin a data transfer. A repeated START condition
is issued identically to a normal START condition.
See Figure 6 for applicable timing.
Bit Write: Transitions of SDA must occur during the
low state of SCL. The data on SDA must remain valid
and unchanged during the entire high pulse of SCL,
plus the setup-and-hold time requirements (Figure
6). Data is shifted into the device during the rising
edge of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount
of setup time (Figure 6) before the next rising edge
of SCL during a bit read. The device shifts out each
bit of data on SDA at the falling edge of the previous
SCL pulse, and the data bit is valid at the rising
edge of the current SCL pulse. Remember that the
master generates all SCL clock pulses, including
when it is reading bits from the slave.
Acknowledgement (ACK and NACK): An
Acknowledgement (ACK) or Not Acknowledge
(NACK) is always the ninth bit transmitted during a
byte transfer. The device receiving data (the master
during a read or the slave during a write operation)
performs an ACK by transmitting a zero during the
ninth bit. A device performs a NACK by transmitting
a 1 during the ninth bit. Timing for the ACK and
NACK is identical to all other bit writes (Figure 6). An
ACK is the acknowledgment that the device is prop-
erly receiving data. A NACK is used to terminate a
read sequence or as an indication that the device is
not receiving data.
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most
significant bit first) plus a 1-bit acknowledgement
from the slave to the master. The 8 bits transmitted
by the master are done according to the bit-write def-
inition, and the acknowledgement is read using the
bit-read definition.
Byte Read: A byte read is an 8-bit information trans-
fer from the slave to the master plus a 1-bit ACK or
NACK from the master to the slave. The 8 bits of
information that are transferred (most significant bit
first) from the slave to the master are read by the
master using the bit-read definition, and the master
transmits an ACK using the bit-write definition to
receive additional data bytes. The master must
NACK the last byte read to terminate communication
so the slave returns control of SDA to the master.
Slave Address Byte: Each slave on the I2C bus
responds to a slave address byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7
bits and the R/W bit in the least significant bit. The
DS4426’s slave address is determined by the state
of the A0 and A1 pins (see Table 1). When the R/W
bit is 0 (such as in 90h), the master is indicating it
will write data to the slave. If R/W = 1 (91h in this
case), the master is indicating it wants to read from
the slave. If an incorrect slave address is written, the
DS4426 assumes the master is communicating with
another I2C device and ignores the communication
until the next START condition is sent.
Memory Address: During an I2C write operation,
the master must transmit a memory address to iden-
tify the memory location where the slave is to store
the data. The memory address is always the second
byte transmitted during a write operation following
the slave address byte.
DS4426
Quad-Channel, I2C-Margining IDACs with
Three Channels of Power-Supply Tracking
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS4426T+ | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 4Ch I2C Migrt w/3 ch P-Sup Track RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DS4426T+T&R | 制造商:Maxim Integrated Products 功能描述: 制造商:Maxim Integrated Products 功能描述:28PIN 4X4 TQFN W/4 IDAC&3CH P/S TRA - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC DAC I2C-MARGINING 4CH 28-TQFN |
| DS4426T+T&R | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 4Ch I2C Migrt w/3 ch P-Sup Track RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DS4426T+TR | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Quad-Channel, I2C-Margining IDACs with Three Channels of Power-Supply Tracking |
| DS443 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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