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參數(shù)資料
| 型號(hào)： | DS4550E+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 18/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC I/O EXPANDER I2C 9B 20TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 接口： | I²C，JTAG |
| 輸入/輸出數(shù)： | 9 |
| 中斷輸出： | 無 |
| 頻率 - 時(shí)鐘： | 400kHz |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 包括： | EEPROM |
Slave Address and Address Pins
The DS4550’s I2C slave address is determined by the
state of the A0, A1, and A2 address pins as shown in
Figure 2. Address pins connected to GND result in a ‘0’
in the corresponding bit position in the slave address.
Conversely, address pins connected to VCC result in a
‘1’ in the corresponding bit positions. I2C communica-
tion is described in detail in a later section.
IEEE 1149.1 JTAG Operation
The DS4550 contains an IEEE 1149.1 compliant JTAG
port in addition to the I2C serial bus. Either can be used
to access the internal memory. However, the device
contains no bus arbitration and hence both busses
cannot be used at the same time. All of the I/O pins on
the DS4550 are IEEE 1149.1 boundary-scan compliant.
I/O_0 to I/O_8 as well as the I2C port pins, contain the
typical JTAG boundary scan cells, which allow the pins
to be polled or forced high/low using standard JTAG
instructions. The DS4550 also contains some exten-
sions to normal JTAG functionality, which allows access
to the internal memory. In particular, the DS4550 has
three device-specific test data registers (Memory
Address, Memory Read, and Memory Write) and three
device-specific instructions (ADDRESS, READ, and
WRITE), which provide memory access.
DS4550
I2C and JTAG Nonvolatile 9-Bit I/O
Expander Plus Memory
_____________________________________________________________________
9
MEMORY ADDRESS REGISTER
[LENGTH = 8 BITS]
MEMORY READ REGISTER
[LENGTH = 8 BITS]
MEMORY WRITE REGISTER
[LENGTH = 8 BITS]
MUX 1
LSB
MSB
TEST REGISTERS
EEPROM
TDO
MUX 2
BOUNDARY SCAN REGISTER
[LENGTH = 33 BITS]
IDENTIFICATION REGISTER
[LENGTH = 32 BITS]
VCC
MSB
RJPU
TDI
TMS
TCK
LSB
BYPASS REGISTER
[LENGTH = 1 BIT]
INSTRUCTION REGISTER
[LENGTH = 4 BITS]
TEST ACCESS PORT
(TAP) CONTROLLER
Figure 3. DS4550 JTAG Block Diagram
*THE SLAVE ADDRESS IS DETERMINED BY
ADDRESS PINS A0, A1, AND A2.
1
MSB
SLAVE
ADDRESS*
READ/WRITE
BIT
LSB
01
0
A2
A1
A0
R/W
Figure 2. DS4550 I2C Slave Address Byte
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| DS4560LS-LO+ | 功能描述:熱插拔功率分布 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
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