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參數(shù)資料
型號(hào)： DS4830T+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 29/30頁(yè)
文件大小： 0K
描述： MCU 16B CTRL CALIBR MON 40-TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
系列： MAXQ®
核心處理器： RISC
芯體尺寸： 16-位
速度： 10MHz
連通性： 3 線，I²C，SPI
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 31
程序存儲(chǔ)器容量： 64KB（32K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 18x13b，D/A 8x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 16-WQFN 裸露焊盤
包裝： 帶卷 (TR)
其它名稱： 90-4830T+TRL
DS4830
Optical Microcontroller
8
Maxim Integrated
SPI DIGITAL InTERFACE SPECIFICATIOn (continued)
(VDD = 2.97V to 3.63V, TA = -40NC to +85NC, unless otherwise noted.) (See Figure 3 and Figure 4.)
ELECTRICAL CHARACTERISTICS: JTAG InTERFACE
(VDD = 2.97V to 3.63V, TA = -40NC to +85NC, unless otherwise noted.) (Figure 5)
note 1: All voltages are referenced to GND. Currents entering the IC are specified as positive, and currents exiting the IC are
specified as negative.
note 2: Maximum current assuming 100% CPU duty cycle.
note 3: This value does not include current in GPIO, SCL, SDA, MDIO, MDI, MCL, REFINA, and REFINB.
note 4: Using internal reference.
note 5: There is one internal oscillator. The oscillator (peripheral clock) goes through a 2:1 divider to create the core clock.
note 6: Guaranteed by design.
note 7: ADC conversions are delayed up to 1.6Fs if the fast comparator is sampling the selected ADC channel. This can cause a
slight decrease in the ADC sampling rate.
note 8: Temperature readings average 64 times.
note 9: Programming time does not include overhead associated with the utility ROM interface.
note 10: fSCL must meet the minimum clock low time plus the rise/fall times.
note 11: This device internally provides a hold time of at least 75ns for the SDA signal (referred to the VIH:MIN of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
note 12: CB—Total capacitance of one bus line in pF.
note 13: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
PARAMETER
SYMBOL
COnDITIOnS
MIn
TYP
MAx
UnITS
SSPIDO Output Valid After
SSPICK Shift Edge Transition
tSOV
2tSPI_RF
ns
SSPICS Inactive
tSSH
tSSPICK +
tSPI_RF
ns
SSPICK Inactive to SSPICS
Rising
tSD
tSPI_RF
ns
SSPIDO Output Disabled After
SSPICS Edge Rise
tSLH
2tSSPICK
+
2tSPI_RF
ns
PARAMETER
SYMBOL
COnDITIOnS
MIn
TYP
MAx
UnITS
JTAG Logic Reference
VREF
VDD/2
V
TCK High Time
tTH
0.5
F
s
TCK Low Time
tTL
0.5
F
s
TCK Low to TDO Output
tTLQ
0.125
F
s
TMS, TDI Input Setup to TCK High
tDVTH
0.25
F
s
TMS, TDI Input Hold After TCK
High
tTHDX
0.25
F
s
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