DS5001FP
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AC CHARACTERISTICS: BYTE-WIDE ADDRESS/DATA BUS TIMING
(VCC = 5V ±10%, TA = 0°C to +70°C.)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
40
Delay to Byte-Wide Address Valid from
CE1
, CE2 , or CE1N Low During Op Code Fetch
tCE1LPA
30
ns
41
Pulse Width of CE 1-4, PE 1-4 or CE1N
tCEPW
4tCLK - 35
ns
42
Byte-Wide Address Hold After CE1 , CE2 , or
CE1N
High During Op Code Fetch
tCE1HPA
2tCLK - 20
ns
43
Byte-Wide Data Setup to CE1 , CE2 , or CE1N
High During Op Code Fetch
tOVCE1H
1tCLK + 40
ns
44
Byte-Wide Data Hold After CE1 , CE2 or CE1N
High During Op Code Fetch
tCE1HOV
0
ns
45
Byte-Wide Address Hold After CE 1-4,
PE
1-4, or CE1N High During MOVX
tCEHDA
4tCLK - 30
ns
46
Delay from Byte-Wide Address Valid
CE
1-4, PE 1-4, or CE1N Low During MOVX
tCELDA
4tCLK - 35
ns
47
Byte-Wide Data Setup to CE 1-4, PE 1-4, or
CE1N
High During MOVX (read)
tDACEH
1tCLK + 40
ns
48
Byte-Wide Data Hold After CE 1-4,
PE
1-4, or CE1N High During MOVX (read)
tCEHDV
0
ns
49
Byte-Wide Address Valid to R/ W Active
During MOVX (write)
tAVRWL
3tCLK - 35
ns
50
Delay from R/ W Low to Valid Data Out
During MOVX (write)
tRWLDV
20
ns
51
Valid Data-Out Hold Time from CE 1-4,
PE
1-4, or CE1N High
tCEHDV
1tCLK - 15
ns
52
Valid Data-Out Hold Time from R/ W High
tRWHDV
0
ns
53
Write Pulse Width (R/ W Low Time)
tRWLPW
6tCLK - 20
ns