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2001 Microchip Technology Inc.
DS39026C-page 259
PIC18CXX2
FIGURE 21-19:
MASTER SSP I2C BUS DATA TIMING
TABLE 21-18: MASTER SSP I2C BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max
Units
Conditions
100
THIGH
Clock high time
100 kHz mode
2(TOSC)(BRG + 1)
—
ms
400 kHz mode
2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
ms
101
TLOW
Clock low time
100 kHz mode
2(TOSC)(BRG + 1)
—
ms
400 kHz mode
2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
ms
102
TR
SDA and SCL
rise time
100 kHz mode
—
1000
ns
CB is specified to be
from 10 to 400 pF
400 kHz mode
20 + 0.1CB
300
ns
1 MHz mode(1)
—
300
ns
103
TF
SDA and SCL
fall time
100 kHz mode
—
300
ns
CB is specified to be
from 10 to 400 pF
400 kHz mode
20 + 0.1CB
300
ns
1 MHz mode(1)
—
100
ns
90
TSU:STA
START condition
setup time
100 kHz mode
2(TOSC)(BRG + 1)
—
ms
Only relevant for
Repeated START
condition
400 kHz mode
2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
ms
91
THD:STA
START condition
hold time
100 kHz mode
2(TOSC)(BRG + 1)
—
ms
After this period the
first clock pulse is
generated
400 kHz mode
2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
ms
106
THD:DAT
Data input
hold time
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
ms
1 MHz mode(1)
TBD
—
ns
107
TSU:DAT
Data input
setup time
100 kHz mode
250
—
ns
(Note 2)
400 kHz mode
100
—
ns
1 MHz mode(1)
TBD
—
ns
92
TSU:STO
STOP condition
setup time
100 kHz mode
2(TOSC)(BRG + 1)
—
ms
400 kHz mode
2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
ms
109
TAA
Output valid from
clock
100 kHz mode
—
3500
ns
400 kHz mode
—
1000
ns
1 MHz mode(1)
——
ns
110
TBUF
Bus free time
100 kHz mode
4.7
—
ms
Time the bus must be
free before a new
transmission can start
400 kHz mode
1.3
—
ms
1 MHz mode(1)
TBD
—
ms
D102
CB
Bus capacitive loading
—
400
pF
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter #107 ≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to
line is released.
Note:
90
91
92
100
101
103
106
107
109
110
102
SCL
SDA
In
SDA
Out