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參數(shù)資料
| 型號： | DS80C323QCG |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 11/38頁 |
| 文件大小： | 434K |
| 代理商： | DS80C323QCG |
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DS80C320/DS80C323
110196 11/38
DATA MEMORY CYCLE STRETCH VALUES
Table 3
CKCON.2–0
MD2
0
0
0
0
1
1
1
1
MEMORY
CYCLES
2
3 (default)
4
5
6
7
8
9
RD or WR STROBE
WIDTH IN CLOCKS
2
4
8
12
16
20
24
28
STROBE WIDTH
TIME @ 25 MHz
80 ns
160 ns
320 ns
480 ns
640 ns
800 ns
960 ns
1120 ns
MD1
0
0
1
1
0
0
1
1
MD0
0
1
0
1
0
1
0
1
DUAL DATA POINTER
Data memory block moves can be accelerated using
the Dual Data Pointer (DPTR). The standard 8032
DPTR is a 16–bit value that is used to address off–chip
data RAM or peripherals. In the DS80C320/DS80C323,
the standard data pointer is called DPTR 0 and is
located at SFR addresses 82h and 83h. These are the
standard locations. No modification of standard code is
needed to use DPTR. The new DPTR is located at SFR
84h and 85h and is called DPTR1. The DPTR Select bit
(DPS) chooses the active pointer and is located at the
LSB of the SFR location 86h. No other bits in register
86h have any effect and are set to 0. The user switches
between data pointers by toggling the LSB of register
86h. The increment (INC) instruction is the fastest way
to accomplish this. All DPTR–related instructions use
the currently selected DPTR for any activity. Therefore
only one instruction is required to switch from a source
to a destination address. Using the Dual–Data Pointer
saves code from needing to save source and destina-
tion addresses when doing a block move. Once loaded,
the software simply switches between DPTR and 1. The
relevant register locations are as follows.
DPL
DPH
DPL1
DPH1
DPS
82h
83h
84h
85h
86h
Low byte original DPTR
High byte original DPTR
Low byte new DPTR
High byte new DPTR
DPTR Select (LSB)
Sample code listed below illustrates the saving from
using the dual DPTR. The example program was origi-
nal code written for an 8051 and requires a total of 1869
machine cycles on the DS80C320/DS80C323. This
takes 299
μ
s to execute at 25 MHz. The new code using
the Dual DPTR requires only 1097 machine cycles tak-
ing 175.5
μ
s. The Dual DPTR saves 772 machine
cycles or 123.5
μ
s for a 64 byte block move. Since each
pass through the loop saves 12 machine cycles when
compared to the single DPTR approach, larger blocks
gain more efficiency using this feature.
64 BYTE BLOCK MOVE WITHOUT DUAL DATA POINTER
; SH and SL are high and low byte source address.
; DH and DL are high and low byte of destination address.
# CYCLES
MOV
MOV
MOV
MOV
MOV
MOV
R5, #64d
DPTR, #SHSL
R1, #SL
R2, #SH
R3, #DL
R4, #DH
; NUMBER OF BYTES TO MOVE
; LOAD SOURCE ADDRESS
; SAVE LOW BYTE OF SOURCE
; SAVE HIGH BYTE OF SOURCE
; SAVE LOW BYTE OF DESTINATION
; SAVE HIGH BYTE OF DESTINATION
2
3
2
2
2
2
MOVE:
; THIS LOOP IS PERFORMED THE NUMBER OF TIMES LOADED INTO R5, IN THIS EXAMPLE 64
MOVX
MOV
MOV
A, @DPTR
R1, DPL
R2, DPH
; READ SOURCE DATA BYTE
; SAVE NEW SOURCE POINTER
;
2
2
2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS80C323-QCG | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:High-Speed Microcontroller User Guide |
| DS80C323-QCL | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:High-Speed Microcontroller User Guide |
| DS80C323-QCR | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:High-Speed Microcontroller User Guide |
| DS80C323-QND | 功能描述:8位微控制器 -MCU High-Speed Low-Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| DS80C323-QND/T&R | 制造商:Maxim Integrated Products 功能描述:H.S. MICRO 44PLCC 18MHZ IND 3V T&R - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC MCU HI SPEED 18MHZ IND 44PLCC 制造商:Maxim Integrated Products 功能描述:8-bit Microcontrollers - MCU High-Speed Low-Power |
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