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| 型號： | DS80C390-FNR |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 44/53頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU CAN DUAL HS IND 64-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS |
| 產(chǎn)品變化通告： | Product Discontinuation 20/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | 80C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | CAN，EBI/EMI，SIO，UART/USART |
| 外圍設(shè)備： | 電源故障復(fù)位，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 4K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.85 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-LQFP |
| 包裝： | 托盤 |
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DS80C390 Dual CAN High-Speed Microprocessor
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CAN INTERRUPTS
The DS80C390 supports three interrupts associated with the CAN controllers. One interrupt is dedicated to each
CAN controller, providing receive/transmit acknowledgments from each of its 15 message centers. The remaining
interrupt, the CAN bus activity interrupt, is used to detect CAN bus activity on the C0RX or C1RX pins.
The message center interrupts are enabled/disabled by individual ETI (transmit) and ERI (receive) enable bits in
the corresponding message control register (located in SFR memory) for each message center. All the message
center interrupts of each CAN module are ORed together into their respective CAN interrupt. The successful
transmission or receipt of a message sets the INTRQ bit in the corresponding message control register (located in
SFR memory). This bit can only be cleared through software. In addition, the global interrupt-enable bit (IE.7) and
the specific CAN interrupt-enable bit, EIE.6 (CAN0) or EIE.5 (CAN1), must be correctly set to acknowledge a
message center interrupt.
Interrupt assertion of error and status conditions associated with the CAN modules is controlled by the ERIE and
STIE bits located in the CAN control registers, C0C and C1C.
ARBITRATION AND MASKING
After a CAN module has ascertained that an incoming message is bit-error-free, the identification field of that
message is then compared against one or more arbitration values to determine if they will be loaded into a
message center. Each enabled message center (see the MSRDY bit in the CAN Message Control Register) is
tested in order from 1 to 15. The first message center to successfully pass the test receives the incoming message
and ends the testing. Using masking registers allows the use of more complex identification schemes, as tests can
be made based on bit patterns rather than an exact match between all bits in the identification field and arbitration
values. Each CAN processor also incorporates a set of five masks to allow messages with different IDs to be
grouped and successfully loaded into a message center. Note that some of these masks are optional as per the
bits shown in the Arbitration/Masking Feature Summary table (Table 14).
There are several possible arbitration tests, varying according to which message center is involved. If all the
enabled tests succeed, the message is loaded into the respective message center. The most basic test, performed
on all messages, compares either 11 (CAN 2.0A) or 29 (CAN 2.0B) bits of the identification field to the appropriate
arbitration register, based on the EX/
ST bit in the CAN 0/1 format register. The MEME bit (C0MxF.1 or C1MxF.1)
controls whether the arbitration and ID registers are compared directly or through a mask register. A special set of
arbitration registers dedicated to message center 15 allows added flexibility in filtering this location.
If desired, further arbitration can be performed by comparing the first two bytes of the data field in each message
against two 8-bit media arbitration register bytes. The MDME bit in the CAN message center format registers
(C0MxF.0 or C1MxF.0) either disables (MDME = 0) arbitration, or enables (MDME = 1) arbitration using the media
ID mask registers 0–1.
If the 11-bit or 29-bit arbitration and the optional media-byte arbitration are successful, the message is loaded into
the respective message center. The format register also allows the microcontroller to program each message
center to function in a receive or transmit mode through the T/
R bit, and to use from 0 to 8 data bytes within the
data field of a message. Note that message center 15 can only be used in a receive mode. To avoid a priority
inversion, the DS80C390 CAN processors are configured to reload the transmit buffer with the message of the
highest priority (lowest message center number) whenever an arbitration is lost or an error condition occurs.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS80C390-FNR+ | 功能描述:8位微控制器 -MCU Dual CAN High-Speed RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| DS80C390-QCR | 功能描述:8位微控制器 -MCU Dual CAN High-Speed RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| DS80C390-QCR+ | 功能描述:8位微控制器 -MCU Dual CAN High-Speed RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| DS80C390-QNR | 功能描述:8位微控制器 -MCU Dual CAN High-Speed RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| DS80C390-QNR+ | 功能描述:8位微控制器 -MCU Dual CAN High-Speed RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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