參數(shù)資料
型號(hào): DS87C520-QCL/T&R
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 29/43頁(yè)
文件大?。?/td> 0K
描述: IC MCU EPROM/ROM 33MHZ HS 44PLCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 500
系列: 87C
核心處理器: 8051
芯體尺寸: 8-位
速度: 33MHz
連通性: EBI/EMI,SIO,UART/USART
外圍設(shè)備: 電源故障復(fù)位,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類型: OTP
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 帶卷 (TR)
DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
35 of 43
EXPLANATION OF AC SYMBOLS
In an effort to remain compatible with the original 8051 family, the DS87C520 and DS83C520 specify
the same parameters as such devices, using the same symbols. For completeness, the following is an
explanation of the symbols.
t
Time
A
Address
C
Clock
D
Input data
H
Logic level high
L
Logic level low
I
Instruction
P
PSEN
Q
Output data
R
RD signal
V
Valid
W
WR signal
X
No longer a valid logic
level
Z
Tri-State
POWER-CYCLE TIMING CHARACTERISTICS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Cycle Startup Time
tCSU
1.8
ms
1
Power-On Reset Delay
tPOR
65,536
tCLCL
2
Note 1:
Startup time for crystals varies with load capacitance and manufacturer. Time shown is for an 11.0592MHz crystal
manufactured by Fox.
Note 2:
Reset delay is a synchronous counter of crystal oscillations after crystal startup. Counting begins when the level
on the XTAL1 pin meets the VIH2 criteria. At 33MHz, this time is 1.99ms.
EPROM PROGRAMMING AND VERIFICATION
(VCC = 4.5V to 5.5V, TA = +21C to +27°C.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Programming Voltage
VPP
12.5
13.0
V
1
Programming Supply Current
IPP
50
mA
Oscillator Frequency
1/tCLCL
4
6
MHz
Address Setup to PROG Low
tAVGL
48tCLCL
Address Hold after PROG
tGHAX
48 tCLCL
Data Setup to PROG Low
tDVGL
48 tCLCL
Data Hold after PROG
tGHDX
48 tCLCL
Enable High to VPP
tEHSH
48 tCLCL
VPP Setup to PROG Low
tSHGL
10
μs
VPP Hold after PROG
tSHGL
10
μs
PROG
Width
tGLGH
90
110
μs
Address to Data Valid
tAVQV
48 tCLCL
Enable Low to Data Valid
tELQV
48 tCLCL
Data Float after Enable
tEHQZ
0
48 tCLCL
PROG
High to PROG Low
tGHGL
10
μs
Note 1:
All voltages are referenced to ground.
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