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參數(shù)資料
| 型號： | DS87C520-WCL |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 16/43頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU EPROM/ROM 33MHZ HS 40CDIP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 10 |
| 系列： | 87C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 33MHz |
| 連通性： | EBI/EMI，SIO，UART/USART |
| 外圍設備： | 電源故障復位，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 16KB（16K x 8） |
| 程序存儲器類型： | EPROM，UV |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 40-CDIP（0.600"，15.24mm）窗口 |
| 包裝： | 管件 |
| 其它名稱： | DS87C520WCL |
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DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
23 of 43
POWER-FAIL INTERRUPT
The voltage reference that sets a precise reset threshold also generates an optional early warning Power-
Fail Interrupt (PFI). When enabled by software, the processor will vector to program memory address
0033h if VCC drops below VPFW. PFI has the highest priority. The PFI enable is in the Watchdog Control
SFR (WDCON–D8h). Setting WDCON.5 to a logic 1 will enable the PFI. Application software can also
read the PFI flag at WDCON.4. A PFI condition sets this bit to a 1. The flag is independent of the
interrupt enable and software must manually clear it.
WATCHDOG TIMER
To prevent software from losing control, the DS87C520/DS83C520 include a programmable Watchdog
Timer. The Watchdog is a free-running timer that sets a flag if allowed to reach a preselected timeout. It
can be (re)started by software.
A typical application is to select the flag as a reset source. When the Watchdog times out, it sets its flag,
which generates reset. Software must restart the timer before it reaches its timeout or the processor is
reset.
Software can select one of four timeout values. Then, it restarts the timer and enables the reset function.
After enabling the reset function, software must then restart the timer before its expiration or hardware
will reset the CPU. Both the Watchdog Reset Enable and the Watchdog Restart control bits are protected
by a “Timed Access” circuit. This prevents errant software from accidentally clearing the Watchdog.
Timeout values are precise since they are a function of the crystal frequency as shown in Table 7. For
reference, the time periods at 33MHz also are shown.
The Watchdog also provides a useful option for systems that do not require a reset circuit. It will set an
interrupt flag 512 clocks before setting the reset flag. Software can optionally enable this interrupt source.
The interrupt is independent of the reset. A common use of the interrupt is during debug, to show
developers where the Watchdog times out. This indicates where the Watchdog must be restarted by
software. The interrupt also can serve as a convenient time-base generator or can wake-up the processor
from power saving modes.
The Watchdog function is controlled by the Clock Control (CKCON-8Eh), Watchdog Control (WDCON-
D8h), and Extended Interrupt Enable (EIE-E8h) SFRs. CKCON.7 and CKCON.6 are WD1 and WD0
respectively and they select the Watchdog timeout period as shown in Table 7.
Table 7. Watchdog Timeout Values
WD1
WD2
INTERRUPT
TIMEOUT
TIME (33 MHz)
RESET TIMEOUT
TIME (33 MHz)
0
217 clocks
3.9718 ms
217 + 512 clocks
3.9874 ms
0
1
220 clocks
31.77 ms
220 + 512 clocks
31.79 ms
1
0
223 clocks
254.20 ms
223 + 512 clocks
254.21 ms
1
226 clocks
2033.60 ms
226 + 512 clocks
2033.62 ms
As shown in Table 7, the Watchdog Timer uses the crystal frequency as a time base. A user selects one of
four counter values to determine the timeout. These clock counter lengths are 217 = 131,072 clocks;
220 = 1,048,576; 223 = 8,388,608 clocks; and 226 = 67,108,864 clocks. The times shown in Table 7 are
with a 33MHz crystal frequency. Once the counter chain has completed a full interrupt count, hardware
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