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參數(shù)資料
| 型號(hào)： | DS87C530-QNL |
| 英文描述： | EPROM MICRO WITH REAL TIME CLOCK |
| 中文描述： | 微型存儲(chǔ)器與實(shí)時(shí)時(shí)鐘 |
| 文件頁數(shù)： | 15/40頁 |
| 文件大?。?/td> | 435K |
| 代理商： | DS87C530-QNL |
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DS87C530
022197 15/40
CRYSTALESS PMM
A major component of power consumption in PMM is
the crystal amplifier circuit. The DS87C530 allows the
user to switch CPU operation to an internal ring oscilla-
tor and turn off the crystal amplifier. The CPU would then
have a clock source of approximately 2–4 MHz, divided
by either 4, 64, or 1024. The ring is not accurate, so soft-
ware can not perform precision timing. However, this
mode allows an additional saving of between 0.5 and
6.0 mA depending on the actual crystal frequency.
While this saving is of little use when running at 4 clocks
per instruction cycle, it makes a major contribution when
running in PMM1 or PMM2.
PMM OPERATION
Software invokes the PMM by setting the appropriate
bits in the SFR area. The basic choices are divider
speed and clock source. There are three speeds (4, 64,
and 1024) and two clock sources (crystal, ring). Both the
decisions and the controls are separate. Software will
typically select the clock speed first. Then, it will perform
the switch to ring operation if desired. Lastly, software
can disable the crystal amplifier if desired.
There are two ways of exiting PMM. Software can
remove the condition by reversing the procedure that
invoked PMM or hardware can (optionally) remove it. To
resume operation at a divide by 4 rate under software
control, simply select 4 clocks per cycle, then crystal
based operation if relevant. When disabling the crystal
as the time base in favor of the ring oscillator, there are
timing restrictions associated with restarting the crystal
operation. Details are described below.
There are three registers containing bits that are con-
cerned with PMM functions. They are Power Manage-
ment Register (PMR; C4h), Status (STATUS; C5h), and
External Interrupt Flag (EXIF; 91h)
Clock Divider
Software can select the instruction cycle rate by select-
ing bits CD1 (PMR.7) and CD0 (PMR.6) as follows:
CD1
0
0
1
1
CD0
0
1
0
1
Cycle rate
Reserved
4 clocks (default)
64 clocks
1024 clocks
The selection of instruction cycle rate will take effect
after a delay of one instruction cycle. Note that the clock
divider choice applies to all functions including timers.
Since baud rates are altered, it will be difficult to conduct
serial communication while in PMM. There are minor
restrictions on accessing the clock selection bits. The
processor must be running in a 4 clock state to select
either 64 (PMM1) or 1024 (PMM2) clocks. This means
software cannot go directly from PMM1 to PMM2 or visa
versa. It must return to a 4 clock rate first.
Switchback
To return to a 4 clock rate from PMM, software can sim-
ply select the CD1 and CD0 clock control bits to the 4
clocks per cycle state. However, the DS87C530 pro-
vides several hardware alternatives for automatic
Switchback. If Switchback is enabled, then the
DS87C530 will automatically return to a 4 clock per
cycle speed when an interrupt occurs from an enabled,
valid external interrupt source. A Switchback will also
occur when a UART detects the beginning of a serial
start bit if the serial receiver is enabled (REN=1). Note
the beginning of a start bit does not generate an inter-
rupt; this occurs on reception of a complete serial word.
The automatic Switchback on detection of a start bit
allows hardware to correct baud rates in time for a
proper serial reception. A switchback will also occur
when a byte is written to the SBUF0 or SBUF1 for trans-
mission.
Switchback is enabled by setting the SWB bit (PMR.5)
to a 1 in software. For an external interrupt, Switchback
will occur only if the interrupt source could really gener-
ate the interrupt. For example, if INT0 is enabled but has
a low priority setting, then Switchback will not occur on
INT0 if the CPU is servicing a high priority interrupt.
Status
Information in the Status register assists decisions
about switching into PMM. This register contains
information about the level of active interrupts and the
activity on the serial ports.
The DS87C530 supports three levels of interrupt prior-
ity. These levels are Power–fail, High, and Low. Bits
STATUS.7–5 indicate the service status of each level. If
PIP (Power–fail Interrupt Priority; STATUS.7) is a 1,
then the processor is servicing this level. If either HIP
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS87C530-QNL+ | 功能描述:8位微控制器 -MCU EPROM MCU w/RTC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| DS87C530Z+ECL | 制造商:Maxim Integrated Products 功能描述:MICRO OTP RTC 33MHZ 52P TQFP PB-FRR - Trays |
| DS87C550 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:EPROM High-Speed Micro with A/D and PWM |
| DS87C550-FCL | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:EPROM High-Speed Micro with A/D and PWM |
| DS87C550-FNL | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:EPROM High-Speed Micro with A/D and PWM |
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