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參數資料
| 型號： | DS89C440-QNG |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 22/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH 32KB 25MHZ 44-PLCC |
| 標準包裝： | 26 |
| 系列： | 89C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 25MHz |
| 連通性： | EBI/EMI，SIO，UART/USART |
| 外圍設備： | 電源故障復位，WDT |
| 輸入/輸出數： | 32 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
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DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers
29 of 46
Page Mode, External Memory Cycle
Page mode retains the basic circuitry requirement for an original 8051 external memory interface, but alters the
configuration of P0 and P2 for the purposes of address output and data I/O during external memory cycles.
Additionally, the functions of ALE and PSEN are altered to support this mode of operation.
Setting the PAGEE (ACON.7) bit to logic 1 enables page mode. Clearing the PAGEE bit to logic 0 disables the
page mode and the external bus structure defaults to the original 8051 expanded bus configuration (nonpage
mode). The DS89C430 supports page mode in two external bus structures. The logic value of the page-mode-
select bits in the ACON register determines the external bus structure and the basic memory cycle in number of
system clocks. Table 6 summarizes this option. The first three selections use the same bus structure but with
different memory cycle time. Setting the select bits to 11b selects another bus structure. Write access to the ACON
register requires a timed access.
Table 6. Page Mode Select
CLOCKS PER MEMORY CYCLE
PAGES1:PAGES0
PAGE-HIT
PAGE-MISS
EXTERNAL BUS STRUCTURE
00
1
2
P0: Primary data bus.
P2: Primary address bus, multiplexing both the upper byte and
lower byte of address.
01
2
4
P0: Primary data bus.
P2: Primary address bus, multiplexing both the upper byte and
lower byte of address.
10
4
8
P0: Primary data bus.
P2: Primary address bus, multiplexing both the upper byte and
lower byte of address.
11
2
4
P0: Lower address byte.
P2: The upper address byte is multiplexed with the data byte.
Note: This setting affects external code fetches only; accessing
the external data memory requires four clock cycles, regardless
of page hit or miss.
The first page mode’s (page mode 1) external bus structure uses P2 as the primary address bus, (multiplexing both
the most significant byte and least significant byte of the address for each external memory cycle) and P0 is used
as the primary data bus. During external code fetches, P0 is held in a high-impedance state by the processor. Op
codes are driven by the external memory onto P0 and latched at the end of the external fetch cycle at the rising
edge of PSEN. During external data read/write operations, P0 functions as the data I/O bus. It is held in a high-
impedance state for external reads from data memory and driven with data during external writes to data memory.
A page miss occurs when the most significant byte of the subsequent address is different from the last
address. The external memory machine cycle can be 2, 4, or 8 system clocks in length for a page miss.
A page hit occurs when the most significant byte of the subsequent address does not change from the last
address. The external memory machine cycle can be 1, 2, or 4 system clocks in length for a page hit.
During a page hit, P2 drives Addr [0–7] of the 16-bit address, while the most significant address byte is held in the
external address latches. PSEN, RD, and WR strobes accordingly for the appropriate operation on the P0 data bus.
There is no ALE assertion for page hits.
相關PDF資料 |
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| DS89C440-MNL | IC MCU FLASH 32KB 33MHZ 40-DIP |
| DS89C440-MNG | IC MCU FLASH 32KB 25MHZ 40-DIP |
| DS89C440-ENL | IC MCU FLASH 32KB 33MHZ 44-TQFP |
| DS89C440-ENG | IC MCU FLASH 32KB 25MHZ 44-TQFP |
| MC9S08GT60ACBE | IC MCU 60K FLASH 4K RAM 42-SDIP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DS89C440-QNL | 功能描述:IC MCU FLASH 32KB 33MHZ 44-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:89C 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:260 系列:73S12xx 核心處理器:80515 芯體尺寸:8-位 速度:24MHz 連通性:I²C，智能卡，UART/USART，USB 外圍設備:LED，POR，WDT 輸入/輸出數:9 程序存儲器容量:64KB（64K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:2K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數據轉換器:- 振蕩器型:內部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-VFQFN 裸露焊盤 包裝:管件 |
| DS89C440-QNL+ | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Ultra-High-Speed Flash Microcontrollers |
| DS89C440-XXX | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Ultra-High-Speed Flash Microcontrollers |
| DS89C450 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Ultra-High-Speed Flash Microcontrollers |
| DS89C450+ENG | 制造商:Maxim Integrated Products 功能描述:MCU 8BIT CISC 64KB FLASH 5V 44TQFP - Trays |
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