參數(shù)資料
型號(hào)： DS89C440-QNL
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 37/46頁(yè)
文件大?。?/td> 0K
描述： IC MCU FLASH 32KB 33MHZ 44-PLCC
標(biāo)準(zhǔn)包裝： 26
系列： 89C
核心處理器： 8051
芯體尺寸： 8-位
速度： 33MHz
連通性： EBI/EMI，SIO，UART/USART
外圍設(shè)備： 電源故障復(fù)位，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 管件
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers
42 of 46
Serial ports and timers track the oscillator cycles per machine cycle when the higher divide ratio of 1024 is
selected, and require the switchback function to automatically return to the divide-by-1 mode for proper operation
when a qualified event occurs. Table 14 summarizes the effect of clock mode on timer operation.
It is possible to enable a receive function on a serial port when incoming data is not present and then change to the
higher divide ratio. An inactive serial port receive/transmission mode requires the receive input pin to remain high
and all outgoing transmissions to be completed. During this inactive receive mode it is possible to change the
clock-divide control bits from a divide by 1 to a 1024 divide ratio. In the case when the serial port is being used to
receive or transmit data, it is very important to validate an attempted change in the clock-divide control bits (read
CD1 and CD0 to verify write was allowed) before proceeding with low-power program functions.
Table 14. Effect of Clock Mode on Timer Operation (In Number of Oscillator Clocks)
OSC CYCLES PER
TIMERS 0, 1, 2 CLOCK
OSC CYCLES PER
TIMER 2 CLOCK
TxMH,TxM
=
BAUD RATE
GENERATION
OSC CYCLES PER
SERIAL PORT CLOCK
MODE 0
OSC CYCLES PER
SERIAL PORT CLOCK
MODE 2
4X/2X, CD1,
CD0
OSC CYCLES
PER MACHINE
CYCLE
00
01
1x
T2MH,T2M = xx
SM2 = 0
SM2 = 1 SMOD = 0
SMOD = 1
100
0.25
12
1
0.25
2
3
1
64
32
000
0.5
12
2
0.5
2
6
2
64
32
x01
1 (reserved)
x10
1 (default)
12
4
1
2
12
4
64
32
x11
1024
12,288 4096
1024
2048
12,288
4096
65,536
32,768
x = Don’t care.
Ring Oscillator
When the system is in stop mode the crystal is disabled. When stop mode is removed, the crystal requires a period
of time to start up and stabilize. To allow the system to begin immediate execution of software following the
removal of the stop mode, the ring oscillator is used to supply a system clock until the crystal startup time is
satisfied. Once this time has passed, the ring oscillator is switched off and the system clock is switched to the
crystal oscillator. This function is programmable and is enabled by setting the RGSL bit (EXIF.1) to logic 1. When it
is logic 0, the processor delays software execution until after the 65,536 crystal clock periods. To allow the
processor to know whether it is being clocked by the ring or by the crystal oscillator, an additional bit—RGMD—
indicates which clock source is being used. When the processor is running from the ring, the clock-divide control
bits (CD1 and CD0 in the PMR register) are locked into the divide-by-1 mode (CD1:CD0 = 10b). The clock-divide
control bits cannot be changed from this state until after the system clock transitions to the crystal oscillator
(RGMD = 0).
Note: The watchdog is connected to the crystal oscillator and continues to run at the external clock rate. The ring
oscillator does not drive it.
Idle Mode
Idle mode suspends the processor by holding the program counter in a static state. No instructions are fetched and
no processing occurs. Setting the IDLE bit (PCON.0) to logic 1 invokes idle mode. The instruction that executes
this step is the last instruction prior to freezing the program counter. Once in idle mode, all resources are
preserved, but all peripheral clocks remain active and the timers, watchdog, serial ports, and power monitor
functions continue to operate, so that the processor can exit the idle mode using any interrupt sources that are
enabled. The oscillator-detect circuit also continues to function when enabled. The IDLE bit is cleared automatically
once the idle mode is exited. On returning from the interrupt vector using the RETI instruction, the next address is
the one that immediately follows the instruction that invoked the idle mode. Any reset of the processor also
removes the idle mode.
相關(guān)PDF資料
PDF描述
DS89C440-QNG IC MCU FLASH 32KB 25MHZ 44-PLCC
DS89C440-MNL IC MCU FLASH 32KB 33MHZ 40-DIP
DS89C440-MNG IC MCU FLASH 32KB 25MHZ 40-DIP
DS89C440-ENL IC MCU FLASH 32KB 33MHZ 44-TQFP
DS89C440-ENG IC MCU FLASH 32KB 25MHZ 44-TQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS89C440-QNL+ 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Ultra-High-Speed Flash Microcontrollers
DS89C440-XXX 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Ultra-High-Speed Flash Microcontrollers
DS89C450 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Ultra-High-Speed Flash Microcontrollers
DS89C450+ENG 制造商:Maxim Integrated Products 功能描述:MCU 8BIT CISC 64KB FLASH 5V 44TQFP - Trays
DS89C450+ENL 制造商:Maxim Integrated Products 功能描述:MCU 8BIT CISC 64KB FLASH 5V 44TQFP - Trays
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*