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參數(shù)資料
| 型號： | DS90LV031ATMTCX |
| 英文描述： | Line Driver |
| 中文描述： | 線路驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 162K |
| 代理商： | DS90LV031ATMTCX |
Applications Information
(Continued)
Fail-Safe Feature:
The LVDS receiver is a high gain, high speed device that
amplifies a small differential signal (20mV) to CMOS logic
levels. Due to the high gain and tight threshold of the re-
ceiver, care should be taken to prevent noise from appearing
as a valid signal.
The receiver’s internal fail-safe circuitry is designed to
source/sink a small amount of current, providing fail-safe
protection (a stable known state of HIGH output voltage) for
floating, terminated or shorted receiver inputs.
1.
Open Input Pins.
The DS90LV012A and DS90LT012A
are single receiver devices. Do not tie the receiver inputs
to ground or any other voltages. The input is biased by
internal high value pull up and pull down resistors to set
the output to a HIGH state. This internal circuitry will
guarantee a HIGH, stable output state for open inputs.
2.
Terminated Input.
If the driver is disconnected (cable
unplugged), or if the driver is in a power-off condition,
the receiver output will again be in a HIGH state, even
with the end of cable 100
termination resistor across
the input pins. The unplugged cable can become a
floating antenna which can pick up noise. If the cable
picks up more than 10mV of differential noise, the re-
ceiver may see the noise as a valid signal and switch. To
insure that any noise is seen as common-mode and not
differential, a balanced interconnect should be used.
Twisted pair cable will offer better balance than flat
ribbon cable.
3.
Shorted Inputs.
If a fault condition occurs that shorts
the receiver inputs together, thus resulting in a 0V differ-
ential input voltage, the receiver output will remain in a
HIGH state. Shorted input fail-safe is not supported
across the common-mode range of the device (GND to
2.4V). It is only supported with inputs shorted and no
external common-mode voltage applied.
External lower value pull up and pull down resistors (for a
stronger bias) may be used to boost fail-safe in the presence
Pin Descriptions
of higher noise levels. The pull up and pull down resistors
should be in the 5k
to 15k
range to minimize loading and
waveform distortion to the driver. The common-mode bias
point should be set to approximately 1.2V (less than 1.75V)
to be compatible with the internal circuitry.
The DS90LV012A and DS90LT012A are compliant to the
originalANSI EIA/TIA-644 specification and is also compliant
to the new ANSI EIA/TIA-644-A specification with the excep-
tion the newly added
I
specification. Due to the internal
fail-safe circuitry,
I
cannot meet the 6μA maximum speci-
fied. This exception will not be relevant unless more than 10
receivers are used.
Additional information on fail-safe biasing of LVDS devices
may be found in AN-1194.
Probing LVDS Transmission Lines:
Always use high impedance (
>
100k
), low capacitance
(
<
2 pF) scope probes with a wide bandwidth (1 GHz)
scope. Improper probing will give deceiving results.
Cables and Connectors, General Comments:
When choosing cable and connectors for LVDS it is impor-
tant to remember:
Use controlled impedance media. The cables and connec-
tors you use should have a matched differential impedance
of about 100
. They should not introduce major impedance
discontinuities.
Balanced cables (e.g. twisted pair) are usually better than
unbalanced cables (ribbon cable, simple coax) for noise
reduction and signal quality. Balanced cables tend to gener-
ate less EMI due to field canceling effects and also tend to
pick up electromagnetic radiation a common-mode (not dif-
ferential mode) noise which is rejected by the receiver.
For cable distances
<
0.5M, most cables can be made to
work effectively. For distances 0.5M
≤
d
≤
10M, CAT 3
(category 3) twisted pair cable works well, is readily available
and relatively inexpensive.
Package Pin Number
SOT23
4
3
5
1
2
Pin Name
Description
LLP
1
3
8
6
2, 7
4, 5
IN
IN+
TTL OUT
V
DD
GND
NC
Inverting receiver input pin
Non-inverting receiver input pin
Receiver output pin
Power supply pin, +3.3V
±
0.3V
Ground pin
No connect
Ordering Information
Operating
Temperature
40C to +85C
Package Type/
Number
MF05A
LDA08A
Order Numbers
DS90LV012ATMF, DS90LT012ATMF
DS90LV012ATLD, DS90LT012ATLD
D
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| DS90LV031ATMTCX/NOPB | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| DS90LV031ATMX | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| DS90LV031ATMX/NOPB | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| DS90LV031AW | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:3V LVDS Quad CMOS Differential Line Driver |
| DS90LV031AWGMLS | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
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