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參數(shù)資料
| 型號： | DSC-11524-234Q |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | DIGITAL TO SYNCHRO OR RESOLVER, DIP36 |
| 封裝： | DDIP-36 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 529K |
| 代理商： | DSC-11524-234Q |
4
Data Device Corporation
www.ddc-web.com
DSC-11524
L-7/08-0
INTRODUCTION
As shown in FIGURE 1, the signal conversion in the DSC-11524
is performed by a high-accuracy Digital-to-Resolver converter
whose SIN and COS outputs have a low scale factor variation as
a function of the digital input angle. This resolver output is either
amplified by scaling amplifiers for resolver output, or is both
amplified and converted to a synchro output by an electronic
Scott-T. In both cases the output line currents can be 15 mA rms
max, which is sufficient for driving S/D converters, solid-state
control transformers and displays. Output power amplifiers will
be required, however, for driving electromechanical devices such
as synchros and resolvers.
The reference conditioner has a differential input with high ac
and DC common mode rejection, so that a reference isolation
transformer will seldom be required. There are two sets of refer-
ence inputs. The RH, RL input provides the maximum synchro or
resolver output voltage for a standard 26 V rms reference input.
The RH, RL input is used to scale the output for other reference
voltage levels. Series resistors can be added to the reference
input as described below, either to accommodate higher refer-
ence levels, or to reduce the output level. The reference condi-
tioner output -R is intended for test purposes. A signal between
6 V and 7.5 V at -R indicates that a reference input signal is pres-
ent.
DIGITAL INPUT
The converter contains three input latches. The input is con-
trolled by LM and LL. Each of these enable the converter to
interface with an 8-bit bus. LM controls bits 1-8 and LL controls
bits 9-16. Ensure that the data is stable for 50ns before enabling
a latch (LL, LM), and allow 100ns for the latch to input the data.
Input Bit Weights are as follows:
BIT 1, MSB = 180 degrees
Bit 16, LSB = 0.0054 degrees (See Table 2)
POWER SUPPLY CYCLING
Power supply cycling of the DDC converter should follow the
guidelines below to avoid any potential problems.
Strictly maintain proper sequencing of supplies and signals per
typical CMOS circuit guidelines:
- Apply power supplies first (+15V, -15V and Ground).
- Apply analog signals last.
The reverse sequence should be followed during power down
of the circuit.
16 BIt DIGItAL wORD (φ) (1 = MSB, 16 = LSB)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0 0 0 0 0 0 0 0
0
0 0
0 0 0 0 1 0 1 0 1
0
1
0
1
0
1 1
0 0 0 1 0 1 0 1 0
1
0
1
0
1
0 1
0 0 1 0 0 0 0 0
0
0 0
0 0 1 0 1 0 1 0
1
0
1
0
1
0
1 1
0 0 0 1 1 1
1 1
1 1 1
1
1 1
1
0 0 1 1 0 1 0 1
0
1
0
1
0
1
0 1
0 1 0 0 0 0 0 0
0
0 0
0 1 0 1 0 1 0 1 0
1
0
1 0
1
0 1
0 1 1 0 0 0 0 0 0
0
0 0
DEGREES (hEx)
0° (0000)
15° (0AAB)
30° (1555)
45° (2000)
60° (2AAB)
75° (3666)
90° (4000)
120° (5555)
135° (6000)
1 0 0 0 0 0 0 0 0
0
0 0
1 0 1 0 1 0 1 0
1
0
1
0
1
0
1 1
1 1 0 0 0 0 0 0 0
0
0 0
1 1 0 0 1 0 1 0 1
0
1
0
1 1
1
1 0 1 0 1 0
1
0
1
0
1
0 1
0 0 0 1 1 1
1 1
1 1 1
1
1 1
1
1 1 1 0 0 0 0 0 0
0
0 0
1 1 1 0 1 0 1 0 1
0
1
0
1
0
1 1
1 1 1 1 0 1 0 1 0
1
0
1
0
1
0 1
1 1 1 1 1 1 1 1 1
1
1 1
180° (8000)
240° (AAAB)
270° (C000)
285° (CAAB)
300° (D555)
315° (E000)
330° (EAAB)
345° (F555)
359° (FFFF)
0
tABLE 2. AnGLES In DEGREES CROSS REFEREnCED tO A
16-BIt DIGItAL wORD
0
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PDF描述 |
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| DSC-11524-234W | DIGITAL TO SYNCHRO OR RESOLVER, DIP36 |
| DSC-11524-234Y | DIGITAL TO SYNCHRO OR RESOLVER, DIP36 |
| DSC-11524-234Z | DIGITAL TO SYNCHRO OR RESOLVER, DIP36 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSC-11524-302 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital-to-Resolver/Synchro Converter |
| DSC-11524-303 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital-to-Resolver/Synchro Converter |
| DSC-11524-304 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital-to-Resolver/Synchro Converter |
| DSC-11524-305 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital-to-Resolver/Synchro Converter |
| DSC1206-100KJI | 制造商:TT Electronics / Welwyn 功能描述:RESISTOR DOUBLE SIDED 100K 1206 CASE |
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