參數(shù)資料
型號: DSP56321VF240
廠商: Freescale Semiconductor
文件頁數(shù): 34/84頁
文件大小: 0K
描述: IC DSP 24BIT 240MHZ 196-BGA
標準包裝: 126
系列: DSP56K/Symphony
類型: 定點
接口: 主機接口,SSI,SCI
時鐘速率: 240MHz
非易失內(nèi)存: ROM(576 B)
芯片上RAM: 576kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.60V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 196-FBGA
供應商設備封裝: 196-MAPBGA(15x15)
包裝: 托盤
DSP56321 Technical Data, Rev. 11
iv
Freescale Semiconductor
Target Applications
DSP56321 applications require high performance, low power, small packaging, and a large amount of internal
memory. The EFCOP can accelerate general filtering applications. Examples include:
Wireless and wireline infrastructure applications
Multi-channel wireless local loop systems
Security encryption systems
Home entertainment systems
DSP resource boards
High-speed modem banks
IP telephony
Internal Memories
192
× 24-bit bootstrap ROM
192 K
× 24-bit RAM total
Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable:
External Memory
Expansion
Data memory expansion to two 256 K
× 24-bit word memory spaces using the standard external address
lines
Program memory expansion to one 256 K
× 24-bit words memory space using the standard external
address lines
External memory expansion port
Chip select logic for glueless interface to static random access memory (SRAMs)
Power Dissipation
Very low-power CMOS design
Wait and Stop low-power standby modes
Fully static design specified to operate down to 0 Hz (dc)
Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-
dependent)
Packaging
Molded array plastic-ball grid array (MAP-BGA) package in lead-free or lead-bearing versions.
Table 1. DSP56321 Features (Continued)
Feature
Description
:
Program RAM
Size
Instruction
Cache Size
X Data RAM
Size*
Y Data RAM
Size*
Instruction
Cache
MSW2
MSW1
MSW0
32 K
× 24-bit
0
80 K
× 24-bit
80 K
× 24-bit
disabled
0
31 K
× 24-bit
1024
× 24-bit
80 K
× 24-bit
80 K
× 24-bit
enabled
0
40 K
× 24-bit
0
76 K
× 24-bit
76 K
× 24-bit
disabled
0
1
39 K
× 24-bit
1024
× 24-bit
76 K
× 24-bit
76 K
× 24-bit
enabled
0
1
48 K
× 24-bit
0
72 K
× 24-bit
72 K
× 24-bit
disabled
0
1
0
47 K
× 24-bit
1024
× 24-bit
72 K
× 24-bit
72 K
× 24-bit
enabled
0
1
0
64 K
× 24-bit
0
64 K
× 24-bit
64 K
× 24-bit
disabled
0
1
63 K
× 24-bit
1024
× 24-bit
64 K
× 24-bit
64 K
× 24-bit
enabled
0
1
72 K
× 24-bit
0
60 K
× 24-bit
60 K
× 24-bit
disabled
1
0
71 K
× 24-bit
1024
× 24-bit
60 K
× 24-bit
60 K
× 24-bit
enabled
1
0
80 K
× 24-bit
0
56 K
× 24-bit
56 K
× 24-bit
disabled
1
0
1
79 K
× 24-bit
1024
× 24-bit
56 K
× 24-bit
56 K
× 24-bit
enabled
1
0
1
96 K
× 24-bit
0
48 K
× 24-bit
48 K
× 24-bit
disabled
1
0
95 K
× 24-bit
1024
× 24-bit
48 K
× 24-bit
48 K
× 24-bit
enabled
1
0
112 K
× 24-bit
0
40 K
× 24-bit
40 K
× 24-bit
disabled
1
111 K
× 24-bit
1024
× 24-bit
40 K
× 24-bit
40 K
× 24-bit
enabled
1
*Includes 12 K
× 24-bit shared memory (that is, 24 K total memory shared by the core and the EFCOP)
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