參數(shù)資料
型號(hào)： DSP56852E
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù)： 7/48頁(yè)
文件大?。?/td> 731K
代理商： DSP56852E
Introduction
56852 Technical Data, Rev. 8
Freescale Semiconductor
7
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56852 are organized into functional groups, as shown in
Table 2-1
and
as illustrated in
Figure 2-1
. In
Table 3-1
, each table row describes the package pin and the signal or
signals present.
1. V
DD
= V
DD CORE,
V
SS
= V
SS CORE,
V
DDIO
= V
DD IO,
V
SSIO
= V
SS IO,
V
DDA
= V
DD ANA,
V
SSA
= V
SS ANA
2. CLKOUT is muxed Address pin A20.
3. Four Address pins are multiplexed with the timer, CS3 and CLKOUT pins.
4. CS3 is multiplexed with external Address Bus pin A19.
5. Mode pins are multiplexed with External Data pins D13-D15 like A17and A18.
6. Four of these pins are multiplexed with SSI.
7. Two of these pins are multiplexed with 2 bits of the External Address Bus A17and A18.
Table 2-1 Functional Group Pin Allocations
Functional Group
Number of Pins
Power (V
DD,
V
DDIO, or
V
DDA
)
10
1
Ground (V
SS,
V
SSIO,
or V
SSA
)
10
1
Phase Lock Loop (PLL) and Clock
2
2
External Bus Signals
39
3
External Chip Select*
3
4
Interrupt and Program Control
3
5
Synchronous Serial Interface (SSI) Port*
6
Serial Communications Interface (SCI) Port*
2
Serial Peripheral Interface (SPI) Port
0
6
Quad Timer Module Port
0
7
JTAG/Enhanced On-Chip Emulation (EOnCE)
6
*Alternately, GPIO pins
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