參數(shù)資料
型號(hào): DSP56F802TA80
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號(hào)控制器
文件頁數(shù): 21/40頁
文件大小: 2472K
代理商: DSP56F802TA80
56F802 Technical Data, Rev. 7
28
Freescale Semiconductor
3.9 Analog-to-Digital Converter (ADC) Characteristics
Table 3-13 ADC Characteristics
Characteristic
Symbol
Min
Typ
Max
Unit
ADC input voltages
VADCIN
01
1. For optimum ADC performance,keep the minimum VADCIN value > 250mV. Inputs less than 250mV volts may convert
to a digital output code of 0 or cause erroneous conversions.
VREF2
2. VREF must be equal to or less than VDDA - 0.3V and must be greater than 2.7V.
V
Resolution
RES
12
12
Bits
Integral Non-Linearity3
3. Measured in 10-90% range.
INL
+/- 4
+/- 5
LSB4
4. LSB = Least Significant Bit.
Differential Non-Linearity
DNL
+/- 0.9
+/- 1
LSB3
Monotonicity
GUARANTEED
ADC internal clock5
5. Guaranteed by characterization.
fADIC
0.5
5
MHz
Conversion range
RAD
VSSA
VDDA
V
Power-up time
tADPU
2.5
msec
Conversion time
tADC
6
tAIC cycles6
6. tAIC = 1/fADIC
Sample time
tADS
1
tAIC cycles6
Input capacitance
CADI
5
pF6
Gain Error (transfer gain)5
EGAIN
1.00
1.10
1.15
Offset Voltage5
VOFFSET
+10
+230
+325
mV
Total Harmonic Distortion5
THD
55
60
dB
Signal-to-Noise plus Distortion5
SINAD
54
56
Effective Number of Bits5
ENOB
8.5
9.5
bit
Spurious Free Dynamic Range5
SFDR
60
65
dB
Spurious Free Dynamic Range
SFDR
65
70
dB
ADC Quiescent Current (both ADCs)
IADC
50
mA
VREF Quiescent Current (both ADCs)
IVREF
12
16.5
mA
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