參數(shù)資料
型號(hào)： DSP56F807VF80
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 5/60頁(yè)
文件大?。?/td> 0K
描述： IC DSP 80MHZ 60K FLASH 160-BGA
標(biāo)準(zhǔn)包裝： 126
系列： 56F8xx
核心處理器： 56800
芯體尺寸： 16-位
速度： 80MHz
連通性： CAN，EBI/EMI，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 136KB（68K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 6K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 160-BGA
包裝： 托盤
GPIO Signals
56F807 Technical Data Technical Data, Rev. 16
Freescale Semiconductor
13
2.6 GPIO Signals
1
RSTO
Output
Reset Output—This output reflects the internal reset state of the
chip.
1
RESET
Input
(Schmitt)
Input
Reset—This input is a direct hardware reset on the processor. When
RESET is asserted low, the device is initialized and placed in the
Reset state. A Schmitt trigger input is used for noise immunity. When
the RESET pin is deasserted, the initial chip operating mode is
latched from the EXTBOOT pin. The internal reset signal will be
deasserted synchronous with the internal clocks, after a fixed number
of internal clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert
RESET, but do not assert TRST.
1
EXTBOOT
Input
(Schmitt)
Input
External Boot—This input is tied to VDD to force device to boot from
off-chip memory. Otherwise, it is tied to VSS.
Table 2-10 Dedicated General Purpose Input/Output (GPIO) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
8
GPIOB0-
GPIOB7
Input
or
Output
Input
Port B GPIO—These eight pins are dedicated General Purpose I/O
(GPIO) pins that can individually be programmed as input or output
pins.
After reset, the default state is GPIO input.
6
GPIOD0-
GPIOD5
Input
or
Output
Input
Port D GPIO—These six pins are dedicated GPIO pins that can
individually be programmed as an input or output pins.
After reset, the default state is GPIO input.
Table 2-9 Interrupt and Program Control Signals (Continued)
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56F807VF80E 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16 BIT HYBRID CONTROLLER RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSP56F807VF80E 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC
DSP56F807VF80J 制造商:Freescale Semiconductor 功能描述:DSP 16BIT - Trays
DSP56F826 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
DSP56F826-827UM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor Users Manual
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