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參數(shù)資料
| 型號(hào)： | DSPB56007FJ66 |
| 英文描述： | DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC |
| 中文描述： | 數(shù)字信號(hào)處理器| 24位|的CMOS | QFP封裝| 80腳|塑料 |
| 文件頁(yè)數(shù)： | 13/83頁(yè) |
| 文件大?。?/td> | 382K |
| 代理商： | DSPB56007FJ66 |
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Signal/Connection Descriptions
Interrupt and Mode Control
MOTOROLA
DSP56007/D
1-7
INTERRUPT AND MODE CONTROL
The interrupt and mode control signals select the DSP’s operating mode as it comes
out of hardware reset and receives interrupt requests from external sources after
reset.
Table 1-7
Interrupt and Mode Control Signals
Signal Name
Signal
Type
State during
Reset
Signal Description
MODA
IRQA
Input
Input (MODA)
Mode Select A
—This input signal has three functions:
to work with the MODB and MODC signals to select
the DSP’s initial operating mode,
to allow an external device to request a DSP
interrupt after internal synchronization, and
to turn on the internal clock generator when the DSP
is in the Stop processing state, causing the DSP to
resume processing.
MODA is read and internally latched in the DSP when the
processor exits the Reset state. The logic state present on the
MODA, MODB, and MODC pins selects the initial DSP
operating mode. Several clock cycles after leaving the Reset
state, the MODA signal changes to the external interrupt
request IRQA. The DSP operating mode can be changed by
software after reset.
External Interrupt Request A (IRQA)
—The IRQA input is a
synchronized external interrupt request. It may be
programmed to be level-sensitive or negative-edge-
triggered. When the signal is edge-triggered, triggering
occurs at a voltage level and is not directly related to the fall
time of the interrupt signal. However, as the fall time of the
interrupt signal increases, the probability that noise on IRQA
will generate multiple interrupts also increases.
While the DSP is in the Stop mode, asserting IRQA gates on
the oscillator and, after a clock stabilization delay, enables
clocks to the processor and peripherals. Hardware reset
causes this input to function as MODA.
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