參數(shù)資料
型號(hào)： DSPIC30F4012-20I/SO
廠商： Microchip Technology
文件頁(yè)數(shù)： 41/238頁(yè)
文件大小： 0K
描述： IC DSPIC MCU/DSP 48K 28SOIC
產(chǎn)品培訓(xùn)模塊： dsPIC30F Quadrature Encoder Interface
Serial Communications using dsPIC30F CAN
Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標(biāo)準(zhǔn)包裝： 27
系列： dsPIC™ 30F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 20 MIPS
連通性： CAN，I²C，SPI，UART/USART
外圍設(shè)備： 高級(jí)欠壓探測(cè)/復(fù)位，電機(jī)控制 PWM，QEI，POR，PWM，WDT
輸入/輸出數(shù)： 20
程序存儲(chǔ)器容量： 48KB（16K x 24）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
配用： XLT28SO-1-ND - SOCKET TRANSITION 28SOIC 300MIL
其它名稱： DSPIC30F401220ISO
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2010 Microchip Technology Inc.
DS70135G-page 135
dsPIC30F4011/4012
19.6.2
PRESCALER SETTING
There is a programmable prescaler with integral values
ranging from 1 to 64 in addition to a fixed divide-by-2 for
clock generation. The Time Quantum (TQ) is a fixed
unit of time derived from the oscillator period, shown in
Equation 19-1, where FCAN is FCY (if the CANCKS bit
is set) or 4 FCY (if CANCKS is cleared).
EQUATION 19-1:
TIME QUANTUM FOR
CLOCK GENERATION
19.6.3
PROPAGATION SEGMENT
This part of the bit time is used to compensate physical
delay times within the network. These delay times con-
sist of the signal propagation time on the bus line and
the internal delay time of the nodes. The propagation
segment can be programmed from 1 TQ to 8 TQ by
setting the PRSEG<2:0> bits (C1CFG2<2:0>).
19.6.4
PHASE SEGMENTS
The phase segments are used to optimally locate the
sampling of the received bit within the transmitted bit
time. The sampling point is between Phase1 Seg and
Phase2 Seg. These segments are lengthened or short-
ened by resynchronization. The end of the Phase1 Seg
determines the sampling point within a bit period. The
segment is programmable from 1 TQ to 8 TQ. Phase2
Seg provides delay to the next transmitted data transi-
tion. The segment is programmable from 1 TQ to 8 TQ,
or it may be defined to be equal to the greater of
Phase1 Seg or the information processing time (2 TQ).
The
Phase1
Seg
is
initialized
by
setting
bits
SEG1PH<2:0> (C1CFG2<5:3>), and Phase2 Seg is
initialized by setting SEG2PH<2:0> (C1CFG2<10:8>).
The following requirement must be fulfilled while setting
the lengths of the phase segments:
Propagation Segment + Phase1 Seg > = Phase2 Seg
19.6.5
SAMPLE POINT
The sample point is the point of time at which the bus
level is read and interpreted as the value of that respec-
tive bit. The location is at the end of Phase1 Seg. If the bit
timing is slow and contains many TQ, it is possible to
specify multiple sampling of the bus line at the sample
point. The level determined by the CAN bus then cor-
responds to the result from the majority decision of three
values. The majority samples are taken at the sample
point and twice before with a distance of TQ/2. The CAN
module allows the user to choose between sampling
three times at the same point, or once at the same point,
by setting or clearing the SAM bit (C1CFG2<6>).
Typically, the sampling of the bit should take place at
about 60-70% through the bit time depending on the
system parameters.
19.6.6
SYNCHRONIZATION
To compensate for phase shifts between the oscillator
frequencies of the different bus stations, each CAN
controller must be able to synchronize to the relevant
signal edge of the incoming signal. When an edge in
the transmitted data is detected, the logic will compare
the location of the edge to the expected time
(synchronous segment). The circuit will then adjust the
values of Phase1 Seg and Phase2 Seg. There are
2 mechanisms used to synchronize.
19.6.6.1
Hard Synchronization
Hard synchronization is only done whenever there is a
‘recessive’ to ‘dominant’ edge during bus Idle, indicating
the start of a message. After hard synchronization, the
bit time counters are restarted with the synchronous
segment. Hard synchronization forces the edge which
has caused the hard synchronization to lie within the
synchronization segment of the restarted bit time. If a
hard synchronization is done, there will not be a
resynchronization within that bit time.
19.6.6.2
Resynchronization
As a result of resynchronization, Phase1 Seg may be
lengthened or Phase2 Seg may be shortened. The
amount of lengthening or shortening of the phase buffer
segment
has
an
upper
bound
known
as
the
synchronization jump width, and is specified by the
SJW<1:0> bits (C1CFG1<7:6>). The value of the
synchronization jump width will be added to Phase1 Seg
or subtracted from Phase2 Seg. The resynchronization
jump width is programmable between 1 TQ and 4 TQ.
The following requirement must be fulfilled while setting
the SJW<1:0> bits:
Phase2 Seg > Synchronization Jump Width
Note:
FCAN must not exceed 30 MHz. If
CANCKS = 0, FCY must not exceed 7.5
MHz.
TQ = 2 (BRP<5:0> + 1)/FCAN
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