參數(shù)資料
型號： DSPIC30F4013-30I/PT
廠商： Microchip Technology
文件頁數(shù)： 118/153頁
文件大小： 0K
描述： IC DSPIC MCU/DSP 48K 44TQFP
產(chǎn)品培訓(xùn)模塊： Serial Communications using dsPIC30F CAN
Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標準包裝： 160
系列： dsPIC™ 30F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 30 MIP
連通性： CAN，I²C，SPI，UART/USART
外圍設(shè)備： AC'97，欠壓檢測/復(fù)位，I²S，POR，PWM，WDT
輸入/輸出數(shù)： 30
程序存儲器容量： 48KB（16K x 24）
程序存儲器類型： 閃存
EEPROM 大小： 1K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 13x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 托盤
產(chǎn)品目錄頁面： 651 (CN2011-ZH PDF)
配用： XLT44PT3-ND - SOCKET TRAN ICE 44MQFP/TQFP
AC164305-ND - MODULE SKT FOR PM3 44TQFP
DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
其它名稱： DSPIC30F401330IPT
2010 Microchip Technology Inc.
DS70138G-page 67
dsPIC30F3014/4013
9.0
TIMER1 MODULE
This section describes the 16-bit general purpose
Timer1 module and associated operational modes.
Figure 9-1 depicts the simplified block diagram of the
16-bit Timer1 module.
The following sections provide a detailed description
including setup and control registers, along with
associated block diagrams for the operational modes of
the timers.
The Timer1 module is a 16-bit timer which can serve as
the time counter for the Real-Time Clock (RTC), or
operate as a free-running interval timer/counter. The
16-bit timer has the following modes:
16-bit Timer
16-bit Synchronous Counter
16-bit Asynchronous Counter
Further, the following operational characteristics are
supported:
Timer gate operation
Selectable prescaler settings
Timer operation during CPU Idle and Sleep
modes
Interrupt on 16-bit Period register match or falling
edge of external gate signal
These operating modes are determined by setting the
appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1
presents a block diagram of the 16-bit timer module.
16-Bit Timer Mode: In the 16-Bit Timer mode, the
timer increments on every instruction cycle up to a
match value preloaded into the Period register, PR1,
then resets to ‘0’ and continues to count.
When the CPU goes into the Idle mode, the timer stops
incrementing unless the TSIDL (T1CON<13>) bit = 0.
If TSIDL = 1, the timer module logic resumes the incre-
menting sequence upon termination of the CPU Idle
mode.
16-Bit Synchronous Counter Mode: In the 16-Bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in PR1,
then resets to ‘0’ and continues.
When the CPU goes into the Idle mode, the timer stops
incrementing unless the respective TSIDL bit = 0. If
TSIDL = 1, the timer module logic resumes the incre-
menting sequence upon termination of the CPU Idle
mode.
16-Bit Asynchronous Counter Mode: In the 16-Bit
Asynchronous Counter mode, the timer increments on
every rising edge of the applied external clock signal.
The timer counts up to a match value preloaded in PR1,
then resets to ‘0’ and continues.
When the timer is configured for the Asynchronous
mode of operation and the CPU goes into the Idle
mode, the timer stops incrementing if TSIDL = 1.
FIGURE 9-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
Note:
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals,
register
descriptions
and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
TON
Sync
SOSCI
SOSCO/
PR1
T1IF
Equal
Comparator x 16
TMR1
Reset
LPOSCEN
Event Flag
1
0
TSYNC
Q
QD
CK
TGATE
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
TGATE
TCY
1
0
T1CK
TC
S
1 x
0 1
TG
A
T
E
0 0
Gate
Sync
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