參數(shù)資料
型號： DSPIC30F5011-30I/PT
廠商： Microchip Technology
文件頁數(shù)： 31/66頁
文件大小： 0K
描述： IC DSPIC MCU/DSP 66K 64TQFP
產品培訓模塊： Asynchronous Stimulus
標準包裝： 160
系列： dsPIC™ 30F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 30 MIP
連通性： CAN，I²C，SPI，UART/USART
外圍設備： AC'97，欠壓檢測/復位，I²S，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 52
程序存儲器容量： 66KB（22K x 24）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
數(shù)據(jù)轉換器： A/D 16x12b
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TQFP
包裝： 托盤
產品目錄頁面： 651 (CN2011-ZH PDF)
配用： XLT64PT5-ND - SOCKET TRAN ICE 64MQFP/TQFP
AC164319-ND - MODULE SKT MPLAB PM3 64TQFP
DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
其它名稱： DSPIC30F501130IPT
DSPIC30F501130IPT-ND
2010 Microchip Technology Inc.
DS70102K-page 37
dsPIC30F Flash Programming Specification
11.4
Flash Memory Programming in
ICSP Mode
Programming in ICSP mode is described in
ming Cycle”. Step-by-step procedures are described
operations must use serial execution, as described in
11.4.1
PROGRAMMING OPERATIONS
Flash memory write and erase operations are
controlled by the NVMCON register. Programming is
performed by setting NVMCON to select the type of
erase operation (Table 11-2) or write operation
(Table 11-3), writing a key sequence to enable the
programming and initiating the programming by setting
the WR control bit, NVMCON<15>.
In ICSP mode, all programming operations are
externally timed. An external 2 ms delay must be used
between setting the WR control bit and clearing the WR
control bit to complete the programming operation.
TABLE 11-2:
NVMCON ERASE
OPERATIONS
NVMCON
Value
Erase Operation
0x407F
Erase all code memory, data memory
(does not erase UNIT ID).
0x4075
Erase 1 row (16 words) of data
EEPROM.
0x4074
Erase 1 word of data EEPROM.
0x4072
Erase all executive memory.
0x4071
Erase 1 row (32 instruction words)
from 1 panel of code memory.
0x406E
Erase Boot Secure and General
Segments, then erase FBS, FSS and
FGS configuration registers.
0x4066
Erase all Data EEPROM allocated to
Boot Segment.
0x405E
Erase Secure and General Segments,
then erase FSS and FGS configuration
registers.
0x4056
Erase all Data EEPROM allocated to
Secure Segment.
0x404E
Erase General Segment, then erase
FGS configuration register.
0x4046
Erase all Data EEPROM allocated to
General Segment.
TABLE 11-3:
NVMCON WRITE
OPERATIONS
NVMCON
Value
Write Operation
0x4008
Write 1 word to configuration
memory.
0x4005
Write 1 row (16 words) to data memory.
0x4004
Write 1 word to data memory.
0x4001
Write 1 row (32 instruction words) into
1 panel of program memory.
11.4.2
UNLOCKING NVMCON FOR
PROGRAMMING
Writes to the WR bit (NVMCON<15>) are locked to
prevent accidental programming from taking place.
Writing a key sequence to the NVMKEY register
unlocks the WR bit and allows it to be written to. The
unlock sequence is performed as follows:
MOV
#0x55, W8
MOV
W8, NVMKEY
MOV
#0xAA, W9
MOV
W9, NVMKEY
Note:
Any working register, or working register
pair, can be used to write the unlock
sequence.
11.4.3
STARTING AND STOPPING A
PROGRAMMING CYCLE
Once the unlock key sequence has been written to the
NVMKEY register, the WR bit (NVMCON<15>) is used
to start and stop an erase or write cycle. Setting the WR
bit initiates the programming cycle. Clearing the WR bit
terminates the programming cycle.
All erase and write cycles must be externally timed. An
external delay must be used between setting and
clearing the WR bit. Starting and stopping a
programming cycle is performed as follows:
BSET
NVMCON, #WR
<Wait 2 ms>
BCLR
NVMCON, #WR
11.5
Erasing Program Memory in
Normal-Voltage Systems
The procedure for erasing program memory (all code
memory, data memory, executive memory and code-
protect bits) consists of setting NVMCON to 0x407F,
unlocking NVMCON for erasing and then executing the
programming cycle. This method of bulk erasing pro-
gram memory only works for systems where VDD is
between 4.5 volts and 5.5 volts. The method for erasing
program memory for systems with a lower VDD (3.0
volts-4.5 volts) is described in Section 6.1 “Erasing
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