- 您現在的位置：買賣IC網 > PDF目錄3831 > DSPIC33FJ128GP202-I/SP (Microchip Technology)IC DSPIC MCU/DSP 128K 28DIP PDF資料下載
參數資料
| 型號： | DSPIC33FJ128GP202-I/SP |
| 廠商： | Microchip Technology |
| 文件頁數： | 26/73頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSPIC MCU/DSP 128K 28DIP |
| 特色產品： | PIC24FJ/33FJ MCUs & dsPIC? DSCs |
| 標準包裝： | 15 |
| 系列： | dsPIC™ 33F |
| 核心處理器： | dsPIC |
| 芯體尺寸： | 16-位 |
| 速度： | 40 MIP |
| 連通性： | I²C，IrDA，LIN，SPI，UART/USART |
| 外圍設備： | AC'97，欠壓檢測/復位，DMA，I²S，POR，PWM，WDT |
| 輸入/輸出數： | 21 |
| 程序存儲器容量： | 128KB（128K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數據轉換器： | A/D 10x10b/12b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 28-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
| 產品目錄頁面： | 653 (CN2011-ZH PDF) |
| 配用： | MA330019-ND - PIM DSPIC33F MC 44P-100P QFN DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2 DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
DS70292G-page 32
2007-2012 Microchip Technology Inc.
3.8.1
MULTIPLIER
The 17-bit x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17-bit x 17-bit
multiplier/scaler is a 33-bit value that is sign-extended
to 40 bits. Integer data is inherently represented as a
signed two’s complement value, where the Most
Significant bit (MSb) is defined as a sign bit. The range
of an N-bit two’s complement integer is -2N-1 to 2N-1 – 1.
For a 16-bit integer, the data range is -32768
(0x8000) to 32767 (0x7FFF) including 0.
For a 32-bit integer, the data range is -
2,147,483,648 (0x8000 0000) to 2,147,483,647
(0x7FFF FFFF).
When the multiplier is configured for fractional
multiplication, the data is represented as a two’s
complement fraction, where the MSb is defined as a
sign bit and the radix point is implied to lie just after the
sign bit (QX format). The range of an N-bit two’s
complement fraction with this implied radix point is -1.0
to (1 – 21-N). For a 16-bit fraction, the Q15 data range
is -1.0 (0x8000) to 0.999969482 (0x7FFF) including 0
and has a precision of 3.01518x10-5. In Fractional
mode, the 16 x 16 multiply operation generates a 1.31
product that has a precision of 4.65661 x 10-10.
The same multiplier is used to support the MCU
multiply instructions, which include integer 16-bit
signed, unsigned and mixed sign multiply operations.
The MUL instruction can be directed to use byte or
word-sized operands. Byte operands direct a 16-bit
result, and word operands direct a 32-bit result to the
specified registers in the W array.
3.8.2
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
The data accumulator consists of a 40-bit adder/
subtracter with automatic sign extension logic. It can
select one of two accumulators (A or B) as its pre-
accumulation
source
and
post-accumulation
destination. For the ADD and LAC instructions, the data
to be accumulated or loaded can be optionally scaled
using the barrel shifter prior to accumulation.
3.8.2.1
Adder/Subtracter, Overflow and
Saturation
The adder/subtracter is a 40-bit adder with an optional
zero input into one side, and either true or complement
data into the other input.
active-high and the other input is true data (not
complemented).
In the case of subtraction, the Carry/Borrow input
is active-low and the other input is complemented.
The adder/subtracter generates Overflow Status bits,
SA/SB and OA/OB, which are latched and reflected in
the STATUS register:
Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block that
controls accumulator data saturation, if selected. It
uses the result of the adder, the Overflow Status bits
described
previously
and
the
SAT<A:B>
(CORCON<7:6>) and ACCSAT (CORCON<4>) mode
control bits to determine when and to what value to
saturate.
Six STATUS register bits support saturation and
overflow:
OA: ACCA overflowed into guard bits
OB: ACCB overflowed into guard bits
SA: ACCA saturated (bit 31 overflow and
saturation)
or
ACCA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
SB: ACCB saturated (bit 31 overflow and
saturation)
or
ACCB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
OAB: Logical OR of OA and OB
SAB: Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic
warning
trap
when
set
and
the
corresponding Overflow Trap Flag Enable bits (OVATE,
OVBTE) in the INTCON1 register are set (refer to
Section 7.0 “Interrupt Controller”). This allows the
user application to take immediate action, for example,
to correct the system gain.
The SA and SB bits are modified each time data
passes through the adder/subtracter, but can only be
cleared by the user application. When set, they indicate
that the accumulator has overflowed its maximum
range (bit 31 for 32-bit saturation or bit 39 for 40-bit sat-
uration) and is saturated (if saturation is enabled).
When saturation is not enabled, SA and SB default to
bit 39 overflow and thus indicate that a catastrophic
overflow has occurred. If the COVTE bit in the
INTCON1 register is set, the SA and SB bits generate
an arithmetic warning trap when saturation is disabled.
相關PDF資料 |
PDF描述 |
|---|---|
| PIC24FJ128GA310-I/BG | MCU 16BIT 128KB FLASH 121TFBGA |
| PIC24HJ128GP204-I/PT | IC PIC MCU FLASH 128K 44TQFP |
| PIC18F8393-I/PT | IC PIC MCU FLASH 4KX16 80TQFP |
| DSPIC33FJ128GP204-I/PT | IC DSPIC MCU/DSP 128K 44TQFP |
| DSPIC33FJ64MC802-I/MM | IC DSPIC MCU/DSP 64K 28-QFN |
相關代理商/技術參數 |
參數描述 |
|---|---|
| dsPIC33FJ128GP202T-I/MM | 功能描述:數字信號處理器和控制器 - DSP, DSC 16B DSC 28LD128KB DMA 40MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數據總線寬度:16 bit 程序存儲器大小:16 KB 數據 RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數量:35 定時器數量:3 設備每秒兆指令數:50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| dsPIC33FJ128GP202T-I/SO | 功能描述:數字信號處理器和控制器 - DSP, DSC 16B DSC 28LD128KB DMA 40MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數據總線寬度:16 bit 程序存儲器大小:16 KB 數據 RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數量:35 定時器數量:3 設備每秒兆指令數:50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| dsPIC33FJ128GP204-E/ML | 功能描述:數字信號處理器和控制器 - DSP, DSC 16b DSC 128KB Flash DMA 40MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數據總線寬度:16 bit 程序存儲器大小:16 KB 數據 RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數量:35 定時器數量:3 設備每秒兆指令數:50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| dsPIC33FJ128GP204-E/PT | 功能描述:數字信號處理器和控制器 - DSP, DSC 16b DSC 128KB Flash DMA 40MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數據總線寬度:16 bit 程序存儲器大小:16 KB 數據 RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數量:35 定時器數量:3 設備每秒兆指令數:50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| dsPIC33FJ128GP204-I/ML | 功能描述:數字信號處理器和控制器 - DSP, DSC 16B DSC 44LD128KB DMA 40MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數據總線寬度:16 bit 程序存儲器大小:16 KB 數據 RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數量:35 定時器數量:3 設備每秒兆指令數:50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復。