參數(shù)資料
型號: DSPIC33FJ128GP706A-E/MR
廠商: Microchip Technology
文件頁數(shù): 19/90頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 128K 64-QFN
標(biāo)準(zhǔn)包裝: 40
系列: dsPIC™ 33F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: CAN,I²C,IrDA,LIN,SPI,UART/USART
外圍設(shè)備: AC'97,欠壓檢測/復(fù)位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 53
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 18x10b/12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 64-VFQFN 裸露焊盤
包裝: 管件
dsPIC33F
DS70155C-page 24
Preliminary
2005 Microchip Technology Inc.
FIGURE 8-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
8.2.2
TIMER2/3
The Timer2/3 module is a 32-bit timer (which can be
configured as two 16-bit timers) with selectable
operating modes. These timers are used by other
peripheral modules, such as:
Input Capture
Output Compare/Simple PWM
Timer2/3 has the following modes:
Two independent 16-bit timers (Timer2 and
Timer3) with Timer and Synchronous Counter
modes
Single 32-Bit Timer
Single 32-Bit Synchronous Counter
Further, the following operational characteristics are
supported:
ADC conversion start trigger
32-bit timer gated by external pulse
Selectable prescaler settings
Timer counter operation during Idle and Sleep
modes
Interrupt on a 32-Bit Period register match
Timer2/3 can use DMA for buffer storage
8.2.3
TIMER4/5, TIMER6/7, TIMER8/9
The Timer4/5, Timer6/7 and Timer8/9 modules are
similar in operation to the Timer2/3 module. Differences
include:
These modules do not support the ADC event
trigger feature
These modules can not be used by other
peripheral modules, such as input capture and
output compare
8.3
Motor Control PWM Module
The Motor Control PWM (MCPWM) module simplifies
the task of generating multiple, synchronized pulse-
width modulated outputs. In particular, the following
power and motion control applications are supported:
Three-Phase AC Induction Motor
Switched Reluctance (SR) Motor
Brushless DC (BLDC) Motor
Uninterrupted Power Supply (UPS)
TON
Sync
SOSCI
SOSCO/
PR1
T1IF
Equal
Comparator x 16
TMR1
Reset
LPOSCEN
Event Flag
1
0
TSYNC
Q
QD
CK
TGATE
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
TGATE
TCY
1
0
T1CK
TCS
1 x
0 1
TG
A
T
E
0 0
Gate
Sync
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