參數(shù)資料
型號： DSPIC33FJ12MC202T-I/SS
廠商： Microchip Technology
文件頁數(shù)： 29/155頁
文件大?。?/td> 0K
描述： IC DSPIC MCU/DSP 12K 28SSOP
產品培訓模塊： Asynchronous Stimulus
標準包裝： 2,100
系列： dsPIC™ 33F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 40 MIP
連通性： I²C，IrDA，SPI，UART/USART
外圍設備： 高級欠壓探測/復位，電機控制 PWM，QEI，POR，PWM，WDT
輸入/輸出數(shù)： 21
程序存儲器容量： 12KB（12K x 8）
程序存儲器類型： 閃存
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉換器： A/D 6x10b/12b
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
包裝： 帶卷 (TR)
2007-2011 Microchip Technology Inc.
DS70265E-page 15
dsPIC33FJ12MC201/202
2.0
GUIDELINES FOR GETTING
STARTED WITH 16-BIT
DIGITAL SIGNAL
CONTROLLERS
2.1
Basic Connection Requirements
Getting started with the dsPIC33FJ12MC201/202
family of 16-bit Digital Signal Controllers (DSC)
requires attention to a minimal set of device pin
connections before proceeding with development. The
following is a list of pin names, which must always be
connected:
All VDD and VSS pins
All AVDD and AVSS pins (regardless if ADC module
is not used)
VCAP
)
MCLR pin
PGECx/PGEDx pins used for In-Circuit Serial
Programming (ICSP) and debugging purposes
OSC1 and OSC2 pins when external oscillator
source is used
Additionally, the following pins may be required:
VREF+/VREF- pins used when external voltage
reference for ADC module is implemented
2.2
Decoupling Capacitors
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD, and
AVSS is required.
Consider the following criteria when using decoupling
capacitors:
Value and type of capacitor: Recommendation
of 0.1 F (100 nF), 10-20V. This capacitor should
be a low-ESR and have resonance frequency in
the range of 20 MHz and higher. It is
recommended that ceramic capacitors be used.
Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 F to 0.001 F. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 F in parallel with 0.001 F.
Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.
Note:
This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33F Family
Reference Manual”
, which is available
Note:
The AVDD and AVSS pins must be
connected independent of the ADC
voltage reference source.
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