參數(shù)資料
型號(hào): DSPIC33FJ16GP304-I/ML
廠商: Microchip Technology
文件頁數(shù): 43/176頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 16K 44QFN
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
特色產(chǎn)品: PIC24FJ/33FJ MCUs & dsPIC? DSCs
標(biāo)準(zhǔn)包裝: 45
系列: dsPIC™ 33F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: I²C,IrDA,LIN,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 35
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VQFN 裸露焊盤
包裝: 管件
產(chǎn)品目錄頁面: 652 (CN2011-ZH PDF)
配用: DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
135
AT89C5131
4136C–USB–04/05
Table 91. USBINT Register
USBINT (S:BDh)
USB Global Interrupt Register
Reset Value = 00h
765
43210
-
WUPCPU
EORINT
SOFINT
-
SPINT
Bit Number
Bit
Mnemonic Description
7-6
-
Reserved
The value read from these bits is always 0. Do not set these bits.
5
WUPCPU
Wake Up CPU Interrupt
This bit is set by hardware when the USB controller is in SUSPEND state and is
re-activated by a non-idle signal FROM USB line (not by an upstream resume).
This triggers a USB interrupt when EWUPCPU is set in Figure 92 on page 136.
When receiving this interrupt, user has to enable all USB clock inputs.
This bit will be cleared by software (USB clocks must be enabled before).
4EORINT
End Of Reset Interrupt
This bit is set by hardware when a End Of Reset has been detected by the USB
controller. This triggers a USB interrupt when EEORINT is set in the Figure 92
This bit will be cleared by software.
3SOFINT
Start of Frame Interrupt
This bit is set by hardware when an USB Start of Frame PID (SOF) has been
detected. This triggers a USB interrupt when ESOFINT is set in the Figure 92
This bit will be cleared by software.
2-
Reserved
The value read from this bit is always 0. Do not set this bit.
1-
Reserved
The value read from this bit is always 0. Do not set this bit.
0SPINT
Suspend Interrupt
This bit is set by hardware when a USB Suspend (Idle bus for three frame
periods: a J state for 3 ms) is detected. This triggers a USB interrupt when
ESPINT is set in see Figure 92 on page 136.
This bit will be cleared by software BEFORE any other USB operation to re-
activate the macro.
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