參數資料
型號: DSPIC33FJ16MC304T-I/ML
廠商: Microchip Technology
文件頁數: 6/76頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 16K 44QFN
產品培訓模塊: Asynchronous Stimulus
標準包裝: 1,600
系列: dsPIC™ 33F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: I²C,IrDA,LIN,SPI,UART/USART
外圍設備: 欠壓檢測/復位,DMA,電機控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數: 35
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數據轉換器: A/D 9x10b/12b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VQFN 裸露焊盤
包裝: 帶卷 (TR)
配用: AC164335-ND - MODULE SKT FOR 10X10 PM3 44TQFP
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
其它名稱: DSPIC33FJ16MC304T-I/MLTR
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
DS70283K-page 14
2007-2012 Microchip Technology Inc.
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
2.2.1
TANK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including DSCs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that con-
nects the power supply source to the device, and the
maximum current drawn by the device in the applica-
tion. In other words, select the tank capacitor so that it
meets the acceptable voltage sag at the device. Typical
values range from 4.7 F to 47 F.
2.3
CPU Logic Filter Capacitor
Connection (VCAP)
A low-ESR (<5 Ohms) capacitor is required on the
VCAP pin, which is used to stabilize the voltage
regulator output voltage. The VCAP pin must not be
connected to VDD, and must have a capacitor between
4.7 F and 10 F, 16V connected to ground. The type
can be ceramic or tantalum. Refer to Section 24.0
for
additional
information.
The placement of this capacitor should be close to the
VCAP. It is recommended that the trace length not
exceed one-quarter inch (6 mm). Refer to Section 21.2
2.4
Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
Device Reset
Device programming and debugging
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
For example, as shown in Figure 2-2, it is
recommended that capacitor C is isolated from the
MCLR pin during programming and debugging
operations.
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
dsPIC33F
V
DD
V
SS
VDD
VSS
VDD
AV
DD
AV
SS
V
DD
V
SS
0.1 F
Ceramic
0.1 F
Ceramic
0.1 F
Ceramic
0.1 F
Ceramic
C
R
VDD
MCLR
0.1 F
Ceramic
V
CAP
L1(1)
R1
10 F
Tantalum
Note 1:
As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 1
Ω and the inductor
capacity greater than 10 mA.
Where:
f
FCNV
2
--------------
=
f
1
2
π LC
()
-----------------------
=
L
1
2
πfC
()
---------------------
2
=
(i.e., ADC conversion rate/2)
Note 1: R
≤ 10 kΩ is recommended. A suggested
starting value is 10 k
Ω. Ensure that the MCLR
pin VIH and VIL specifications are met.
2: R1
≤ 470W will limit any current flowing into
MCLR from the external capacitor C, in the
event of MCLR pin breakdown, due to Elec-
trostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
C
R1(2)
R(1)
VDD
MCLR
dsPIC33F
JP
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