參數(shù)資料
型號： DSPIC33FJ16MC304T-I/PT
廠商： Microchip Technology
文件頁數(shù)： 60/76頁
文件大?。?/td> 0K
描述： IC DSPIC MCU/DSP 16K 44TQFP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
標準包裝： 1,200
系列： dsPIC™ 33F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 40 MIP
連通性： I²C，IrDA，LIN，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，DMA，電機控制 PWM，QEI，POR，PWM，WDT
輸入/輸出數(shù)： 35
程序存儲器容量： 16KB（16K x 8）
程序存儲器類型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 9x10b/12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 帶卷 (TR)
配用： DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
其它名稱： DSPIC33FJ16MC304T-I/PTTR
2007-2012 Microchip Technology Inc.
DS70283K-page 63
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
6.2
Reset Control Registers
REGISTER 6-1:
RCON: RESET CONTROL REGISTER(1)
R/W-0
U-0
R/W-0
TRAPR
IOPUWR
—
—CM
VREGS
bit 15
bit 8
R/W-0
R/W-1
EXTR
SWR
SWDTEN(2)
WDTO
SLEEP
IDLE
BOR
POR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
TRAPR: Trap Reset Flag bit
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
bit 14
IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an
Address Pointer caused a Reset
0 = An illegal opcode or uninitialized W Reset has not occurred
bit 13-10
Unimplemented: Read as ‘0’
bit 9
CM: Configuration Mismatch Flag bit
1 = A configuration mismatch Reset has occurred
0 = A configuration mismatch Reset has NOT occurred
bit 8
VREGS: Voltage Regulator Standby During Sleep bit
1 = Voltage regulator is active during Sleep
0 = Voltage regulator goes into Standby mode during Sleep
bit 7
EXTR: External Reset (MCLR) Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
bit 6
SWR: Software Reset (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
bit 5
SWDTEN: Software Enable/Disable of WDT bit(2)
1 = WDT is enabled
0 = WDT is disabled
bit 4
WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
bit 3
SLEEP: Wake-up from Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
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