參數(shù)資料
型號: DSPIC33FJ256GP710-I/PT
廠商: Microchip Technology
文件頁數(shù): 15/90頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 256K 100TQFP
產品培訓模塊: dsPIC33F DMAC
Introduction to dsPIC33F Architecture Part 1
Asynchronous Stimulus
Introduction to dsPIC33F Architecture Part 2
特色產品: PIC24FJ/33FJ MCUs & dsPIC? DSCs
標準包裝: 119
系列: dsPIC™ 33F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: CAN,I²C,IrDA,LIN,SPI,UART/USART
外圍設備: AC'97,欠壓檢測/復位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 85
程序存儲器容量: 256KB(256K x 8)
程序存儲器類型: 閃存
RAM 容量: 30K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 32x10b/12b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TQFP
包裝: 托盤
產品目錄頁面: 654 (CN2011-ZH PDF)
配用: 876-1001-ND - DSPIC33 BREAKOUT BOARD
AC164333-ND - MODULE SKT FOR PM3 100QFP
DM300024-ND - KIT DEMO DSPICDEM 1.1
DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
MA330012-ND - MODULE DSPIC33 100P TO 84QFP
MA330011-ND - MODULE DSPIC33 100P TO 100QFP
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
dsPIC33F
DS70155C-page 20
Preliminary
2005 Microchip Technology Inc.
FIGURE 6-1:
OSCILLATOR SYSTEM BLOCK DIAGRAM
6.2
Power-on Reset
When a supply voltage is applied to the device, a
Power-on Reset is generated. A new Power-on Reset
event is generated if the supply voltage falls below the
device threshold voltage (VPOR). An internal POR
pulse is generated when the rising supply voltage
crosses the POR circuit threshold voltage.
6.3
Oscillator Start-up Timer/Stabilizer
(OST)
An Oscillator Start-up Timer (OST) is included to
ensure that a crystal oscillator (or ceramic resonator)
has started and stabilized. The OST is a simple, 10-bit
counter that counts 1024 TOSC cycles before releasing
the oscillator clock to the rest of the system. The time-
out period is designated as TOST. The TOST time is
involved every time the oscillator has to restart (i.e., on
Power-on Reset (POR) and wake-up from Sleep). The
Oscillator Start-up Timer is applied to the LP oscillator,
XT and HS modes (upon wake-up from Sleep, POR
and BOR) for the primary oscillator.
6.4
Watchdog Timer (WDT)
The primary function of the Watchdog Timer (WDT) is
to reset the processor in the event of a software
malfunction. The WDT is a free-running timer that runs
off the on-chip LPRC oscillator, requiring no external
component. The WDT continues to operate even if the
main processor clock (e.g., the crystal oscillator) fails.
The Watchdog Timer can be “Enabled” or “Disabled”
either through a configuration bit (FWDTEN) in the
Configuration
register,
or
through
an
SFR
bit
(SWDTEN).
Any device programmer capable of programming
dsPIC DSC devices (such as Microchip’s MPLAB
PM3 Programmer) allows programming of this and
other configuration bits to the desired state. If enabled,
the WDT increments until it overflows or “times out”. A
WDT time-out forces a device Reset (except during
Sleep).
OSC1
Secondary
Oscillator
32 kHz
PLL
Module
Clock
Switching
and
Control
Block
OSC2
SOSCO
SOSCI
FOSC
Primary Osc
Secondary Osc
To Timer1
Internal Fast
RC (FRC)
Oscillator
Internal Low-Power
RC (LPRC)
Oscillator
Primary
Oscillator
FCY
Divide by 4
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