參數(shù)資料
型號: DSPIC33FJ256MC510-I/PF
廠商: Microchip Technology
文件頁數(shù): 47/136頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 256K 100TQFP
產(chǎn)品培訓(xùn)模塊: dsPIC33F DMAC
Introduction to dsPIC33F Architecture Part 1
Asynchronous Stimulus
Introduction to dsPIC33F Architecture Part 2
特色產(chǎn)品: PIC24FJ/33FJ MCUs & dsPIC? DSCs
標(biāo)準(zhǔn)包裝: 90
系列: dsPIC™ 33F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: CAN,I²C,IrDA,LIN,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,電機控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數(shù): 85
程序存儲器容量: 256KB(256K x 8)
程序存儲器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 24x10b/12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 654 (CN2011-ZH PDF)
配用: MA330013-ND - MODULE PLUG-IN DSPIC33 100TQFP
DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
AC164323-ND - MODULE SKT FOR 100TQFP
2009 Microchip Technology Inc.
DS70287C-page 15
dsPIC33FJXXXMCX06/X08/X10
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin Name
Pin
Type
Buffer
Type
Description
AN0-AN31
I
Analog
Analog input channels.
AVDD
P
Positive supply for analog modules. This pin must be connected at all times.
AVSS
P
Ground reference for analog modules.
CLKI
CLKO
I
O
ST/CMOS
External clock source input. Always associated with OSC1 pin function.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes. Always associated
with OSC2 pin function.
CN0-CN23
I
ST
Input change notification inputs.
Can be software programmed for internal weak pull-ups on all inputs.
C1RX
C1TX
C2RX
C2TX
I
O
I
O
ST
ST
ECAN1 bus receive pin.
ECAN1 bus transmit pin.
ECAN2 bus receive pin.
ECAN2 bus transmit pin.
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
I
I/O
I
I/O
I
ST
Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.
Data I/O pin for programming/debugging communication channel 3.
Clock input pin for programming/debugging communication channel 3.
IC1-IC8
I
ST
Capture inputs 1 through 8.
INDX
QEA
QEB
UPDN
I
O
ST
CMOS
Quadrature Encoder Index Pulse input.
Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External
Clock/Gate input in Timer mode.
Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External
Clock/Gate input in Timer mode.
Position Up/Down Counter Direction State.
INT0
INT1
INT2
INT3
INT4
I
ST
External interrupt 0.
External interrupt 1.
External interrupt 2.
External interrupt 3.
External interrupt 4.
FLTA
FLTB
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
PWM4L
PWM4H
I
O
ST
PWM Fault A input.
PWM Fault B input.
PWM 1 low output.
PWM 1 high output.
PWM 2 low output.
PWM 2 high output.
PWM 3 low output.
PWM 3 high output.
PWM 4 low output.
PWM 4 high output.
MCLR
I/P
ST
Master Clear (Reset) input. This pin is an active-low Reset to the device.
OCFA
OCFB
OC1-OC8
I
O
ST
Compare Fault A input (for Compare Channels 1, 2, 3 and 4).
Compare Fault B input (for Compare Channels 5, 6, 7 and 8).
Compare outputs 1 through 8.
OSC1
OSC2
I
I/O
ST/CMOS
Oscillator crystal input. ST buffer when configured in RC mode;
CMOS otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
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