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| 型號： | DSPIC33FJ256MC710-I/PT |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 13/90頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSPIC MCU/DSP 256K 100TQFP |
| 產(chǎn)品培訓(xùn)模塊： | dsPIC33F DMAC Introduction to dsPIC33F Architecture Part 1 Asynchronous Stimulus Introduction to dsPIC33F Architecture Part 2 |
| 特色產(chǎn)品： | PIC24FJ/33FJ MCUs & dsPIC? DSCs |
| 標(biāo)準(zhǔn)包裝： | 119 |
| 系列： | dsPIC™ 33F |
| 核心處理器： | dsPIC |
| 芯體尺寸： | 16-位 |
| 速度： | 40 MIP |
| 連通性： | CAN，I²C，IrDA，LIN，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，DMA，電機(jī)控制 PWM，QEI，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 85 |
| 程序存儲器容量： | 256KB（256K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 30K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 24x10b/12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 654 (CN2011-ZH PDF) |
| 配用： | 876-1001-ND - DSPIC33 BREAKOUT BOARD AC164333-ND - MODULE SKT FOR PM3 100QFP MA330013-ND - MODULE PLUG-IN DSPIC33 100TQFP DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2 DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32 |
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dsPIC33F
DS70155C-page 18
Preliminary
2005 Microchip Technology Inc.
5.1
Interrupt Priority
Each interrupt source can be user-assigned to one of
8 priority levels, 0 through 7. Levels 7 and 1 represent
the
highest
and
lowest
maskable
priorities,
respectively. A priority level of 0 disables the interrupt.
Since more than one interrupt request source may be
assigned to a user-specified priority level, a means is
provided to assign priority within a given level. This
method is called “Natural Order Priority”.
The Natural Order Priority of an interrupt is numerically
identical to its vector number. The Natural Order
Priority scheme has 0 as the highest priority and 74 as
the lowest priority.
The ability for the user to assign every interrupt to one
of eight priority levels implies that the user can assign
a very high overall priority level to an interrupt with a
low Natural Order Priority, thereby providing much
flexibility in designing applications that use a large
number of peripherals.
5.2
Interrupt Nesting
Interrupts, by default, are nestable. Any ISR that is in
progress may be interrupted by another source of
interrupt with a higher user-assigned priority level.
Interrupt nesting may be optionally disabled by
setting the NSTDIS control bit (INTCON1<15>).
When the NSTDIS control bit is set, all interrupts in
progress will force the CPU priority to level 7 by
setting IPL<2:0> = 111. This action will effectively
mask all other sources of interrupt until a RETFIE
instruction is executed. When interrupt nesting is
disabled, the user-assigned interrupt priority levels
will have no effect, except to resolve conflicts
between simultaneous pending interrupts.
The IPL<2:0> bits become read-only when interrupt
nesting is disabled. This prevents the user software
from setting IPL<2:0> to a lower value, which would
effectively re-enable interrupt nesting.
5.3
Traps
Traps can be considered as non-maskable, nestable
interrupts that adhere to a fixed priority structure.
Traps are intended to provide the user a means to
correct erroneous operation during debug and when
operating within the application. If the user does not
intend to take corrective action in the event of a trap
error condition, these vectors must be loaded with the
address of a software routine that will reset the device.
Otherwise, the trap vector is programmed with the
address of a service routine that will correct the trap
condition.
The dsPIC33F has four implemented sources of
non-maskable traps:
Oscillator Failure Trap
Address Error Trap
Stack Error Trap
Math Error Trap
DMA Trap
Many of these trap conditions can only be detected
when they happen. Consequently, the instruction that
caused the trap is allowed to complete before
exception processing begins. Therefore, the user may
have to correct the action of the instruction that
caused the trap.
Each trap source has a fixed priority as defined by its
position in the IVT. An oscillator failure trap has the
highest priority, while an arithmetic error trap has the
lowest priority.
Table 5-2 contains information about the trap vector.
5.4
Generating a Software Interrupt
Any available interrupt can be manually generated by
user software (even if the corresponding peripheral is
disabled), simply by enabling the interrupt and then
setting the interrupt flag bit when required.
TABLE 5-2:
TRAP VECTORS
Vector Number
IVT Address
AIVT Address
Trap Source
0
0x000004
0x000084
Reserved
1
0x000006
0x000086
Oscillator Failure
2
0x000008
0x000088
Address Error
3
0x00000A
0x00008A
Stack Error
4
0x00000C
0x00008C
Math Error
5
0x00000E
0x00008E
DMA Error Trap
6
0x000010
0x000090
Reserved
7
0x000012
0x000092
Reserved
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| dsPIC33FJ256MC710T-I/PF | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 256KB FL 30720bytes RAM 40MIPS 85I/O RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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