參數(shù)資料
型號： DSPIC33FJ32GP204T-I/PT
廠商： Microchip Technology
文件頁數(shù)： 42/176頁
文件大?。?/td> 0K
描述： IC DSPIC MCU/DSP 32K 44TQFP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
標(biāo)準(zhǔn)包裝： 1,200
系列： dsPIC™ 33F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 40 MIP
連通性： I²C，IrDA，LIN，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 35
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 13x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 帶卷 (TR)
配用： DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
其它名稱： DSPIC33FJ32GP204T-I/PTTR
134
AT89C5131
4136C–USB–04/05
USB Registers
Table 90. USBCON Register
USBCON (S:BCh)
USB Global Control Register
Reset Value = 00h
765
43210
USBE
SUSPCLK
SDRMWUP
DETACH
UPRSM
RMWUPE
CONFG
FADDEN
Bit Number
Bit Mnemonic
Description
7USBE
USB Enable
Set this bit to enable the USB controller.
Clear this bit to disable and reset the USB controller, to disable the USB
transceiver an to disable the USB controller clock inputs.
6SUSPCLK
Suspend USB Clock
Set this bit to disable the 48 MHz clock input (Resume Detection is still
active).
Clear this bit to enable the 48 MHz clock input.
5
SDRMWUP
Send Remote Wake Up
Set this bit to force an external interrupt on the USB controller for Remote
Wake UP purpose.
An upstream resume is send only if the bit RMWUPE is set, all USB clocks
are enabled AND the USB bus was in SUSPEND state for at least 5 ms.
See UPRSM below.
This bit is cleared by software.
4
DETACH
Detach Command
Set this bit to simulate a Detach on the USB line. The V
REF pin is then in a
floating state.
Clear this bit to maintain VREF at 3.3V.
3UPRSM
Upstream Resume (read only)
This bit is set by hardware when SDRMWUP has been set and if RMWUPE
is enabled.
This bit is cleared by hardware after the upstream resume has been sent.
2RMWUPE
Remote Wake-Up Enable
Set this bit to enabled request an upstream resume signaling to the host.
Clear this bit otherwise.
Note: Do not set this bit if the host has not set the
DEVICE_REMOTE_WAKEUP feature for the device.
1CONFG
Configured
This bit will be set by the device firmware after a SET_CONFIGURATION
request with a non-zero value has been correctly processed.
It will be cleared by the device firmware when a SET_CONFIGURATION
request with a zero value is received. It is cleared by hardware on hardware
reset or when an USB reset is detected on the bus (SE0 state for at least 32
Full Speed bit times: typically 2.7
s).
0
FADDEN
Function Address Enable
This bit will be set by the device firmware after a successful status phase of
a SET_ADDRESS transaction.
It will not be cleared afterwards by the device firmware. It is cleared by
hardware on hardware reset or when an USB reset is received (see above).
When this bit is cleared, the default function address is used (0).
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