參數(shù)資料
型號(hào)： DT28F160F3B120
廠商： INTEL CORP
元件分類： DRAM
英文描述： FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT
中文描述： 1M X 16 FLASH 2.7V PROM, 120 ns, PDSO56
封裝： 16 X 23.70 MM, SSOP-56
文件頁數(shù)： 8/47頁
文件大?。?/td> 277K
代理商： DT28F160F3B120
FAST BOOT BLOCK DATASHEET
E
8
PRODUCT PREVIEW
Table 1. Pin Descriptions
Sym
Type
Name and Function
A
0
–A
19
INPUT
ADDRESS INPUTS:
Inputs for addresses during read and write operations.
Addresses are internally latched during read and write cycles.
8-Mbit: A
0
–18
, 16-Mbit: A
0–19
DQ
0
–
DQ
15
INPUT/
OUTPUT
DATA INPUT/OUTPUTS:
Inputs data and commands during write cycles, outputs
data during memory array, status register (DQ
0
–DQ
7
), and identifier code read
cycles. Data pins float to high-impedance when the chip is deselected or outputs
are disabled. Data is internally latched during a write cycle.
CLK
INPUT
CLOCK:
Synchronizes the flash memory to the system operating frequency during
synchronous burst-mode read operations. When configured for synchronous burst-
mode reads, address is latched on the first rising (or falling, depending upon the
read configuration register setting) CLK edge when ADV# is active or upon a rising
ADV# edge, whichever occurs first. CLK is ignored during asynchronous page-
mode read and write operations.
ADV#
INPUT
ADDRESS VALID:
Indicates that a valid address is present on the address inputs.
Addresses are latched on the rising edge of ADV# during read and write
operations. ADV# may be tied active during asynchronous read and write
operations.
CE#
INPUT
CHIP ENABLE:
Activates the device’s control logic, input buffers, decoders, and
sense amplifiers. CE#-high deselects the device and reduces power consumption
to standby levels.
RST#
INPUT
RESET:
When driven low, RST# inhibits write operations which provides data
protection during power transitions, and it resets internal automation. RST#-high
enables normal operation. Exit from reset sets the device to asynchronous read
array mode.
OE#
INPUT
OUTPUT ENABLE:
Gates data outputs during a read cycle.
WE#
INPUT
WRITE ENABLE:
Controls writes to the CUI and array. Addresses and data are
latched on the rising edge of the WE# pulse.
WP#
INPUT
WRITE PROTECTION:
Provides a method for locking and unlocking all main
blocks and two parameter blocks.
When WP# is at logic low, lockable blocks are locked. If a program or erase
operation is attempted on a locked block, SR.1 and either SR.4 [program] or SR.5
[block erase] will be set to indicate the operation failed.
When WP# is at logic high, the lockable blocks are unlocked and can be
programmed or erased.
WAIT#
OUTPUT
WAIT:
Provides data valid feedback when configured for synchronous burst-mode
and the burst length is set to continuous. This signal is gated by OE# and CE# and
is internally pull-up to V
CCQ
via a resistor. WAIT# from several components can be
tied together to form one system WAIT# signal.
相關(guān)PDF資料
PDF描述
DT28F160F3B95 FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT
DT28F160F3T120 FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT
DT28F160F3T95 FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT
DT28F800F3B120 FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT
DT28F800F3B95 FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DT28F160F3B95 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT
DT28F160F3T120 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT
DT28F160F3T95 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT
DT28F160S3-100 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:WORD-WIDE FlashFile MEMORY FAMILY
DT28F160S3-120 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:WORD-WIDE FlashFile MEMORY FAMILY
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*