參數(shù)資料
型號(hào)： DT28F160S3-100
廠商： INTEL CORP
元件分類： DRAM
英文描述： 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor
中文描述： 2M X 8 FLASH 2.7V PROM, 100 ns, PDSO56
封裝： 16 X 23.70 MM, SSOP-56
文件頁數(shù)： 14/52頁
文件大?。?/td> 1262K
代理商： DT28F160S3-100
28F160S3, 28F320S3
E
14
ADVANCE INFORMATION
Table 2. Bus Operations
Mode
Notes
RP#
CE
0
#
CE
1
# OE#
(11)
WE#
(11)
Address
V
PP
DQ
(8)
STS
(3)
Read
1,2
V
IH
V
IL
V
IL
V
IL
V
IH
X
X
D
OUT
X
Output Disable
V
IH
V
IL
V
IL
V
IH
V
IH
X
X
High Z
X
Standby
V
IH
V
IL
V
IH
V
IH
V
IH
V
IL
V
IH
X
X
X
X
High Z
X
Reset/Power-
Down Mode
10
V
IL
X
X
X
X
X
X
High Z
High Z
(9)
Read Identifier
Codes
4
V
IH
V
IL
V
IL
V
IL
V
IH
See
Figure 6
X
D
OUT
High Z
(9)
Read Query
5
V
IH
V
IL
V
IL
V
IL
V
IH
See Table 6
X
D
OUT
High Z
(9)
Write
3,6,7
V
IH
V
IL
V
IL
V
IH
V
IL
X
V
PPH1/2
D
IN
X
NOTES:
1. Refer to Table 19. When V
PP
≤
V
PPLK
, memory contents can be read, but not altered.
2. X can be V
IL
or V
IH
for control and address input pins and V
PPLK
or V
PPH1/2
for V
PP
. See Table 19, for V
PPLK
and V
PPH1/2
voltages.
3. STS in level RY/BY# mode (default) is V
OL
when the WSM is executing internal block erase, programming, or lock-bit
configuration algorithms. It is V
OH
when the WSM is not busy, in block erase suspend mode (with programming inactive),
program suspend mode, or deep power-down mode.
4. See Section 4.3 for read identifier code data.
5. See Section 4.2 for read query data.
6. Command writes involving block erase, write, or lock-bit configuration are reliably executed when V
PP
= V
PPH1/2
and
V
CC
= V
CC1/2
(see Section 6.2).
7. Refer to Table 3 for valid D
IN
during a write operation.
8. DQ refers to DQ
0
–7
if BYTE# is low and DQ
0–15
if BYTE# is high.
9. High Z will be V
OH
with an external pull-up resistor.
10.
RP# at GND ± 0.2V ensures the lowest deep power-down current.
11. OE# = V
IL
and WE# = V
IL
concurrently is an undefined state and should not be attempted.
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