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參數(shù)資料
| 型號： | E28F256J3C-115 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel StrataFlash Memory (J3) |
| 中文描述： | 英特爾StrataFlash存儲器（J3） |
| 文件頁數(shù)： | 9/72頁 |
| 文件大?。?/td> | 905K |
| 代理商： | E28F256J3C-115 |
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256-Mbit J3 (x8/x16)
Datasheet
9
suspended (and programming is inactive), program is suspended, or the device is in reset/power-
down mode. Additionally, the configuration command allows the STS signal to be configured to
pulse on completion of programming and/or block erases.
Three CE signals are used to enable and disable the device. A unique CE logic design (see
Table 13, “Chip Enable Truth Table” on page 33
) reduces decoder logic typically required for
multi-chip designs. External logic is not required when designing a single chip, a dual chip, or a 4-
chip miniature card or SIMM module.
The BYTE# signal allows either x8 or x16 read/writes to the device. BYTE#-low selects 8-bit
mode; address A0 selects between the low byte and high byte. BYTE#-high enables 16-bit
operation; address A1 becomes the lowest order address and address A0 is not used (don’t care). A
device block diagram is shown in Figure 4 on page 14.
When the device is disabled (see
Table 13 on page 33
), with CEx at V
IH
and RP# at V
IH
, the
standby mode is enabled. When RP# is at V
IL
, a further power-down mode is enabled which
minimizes power consumption and provides write protection during reset. A reset time (t
PHQV
) is
required from RP# going high until data outputs are valid. Likewise, the device has a wake time
(t
PHWL
) from RP#-high until writes to the CUI are recognized. With RP# at V
IL
, the WSM is reset
and the Status Register is cleared.
2.1
Block Diagram
Figure 1. 3 Volt Intel StrataFlash
Memory Block Diagram
32-Mbit: Thirty-two
64-Mbit: Sixty-four
128-Mbit: One-hundred
twenty-eight
128-Kbyte Blocks
Input Buffer
O
L
Y-Gating
Program/Erase
Voltage Switch
Data
Comparator
Status
Register
Identifier
Register
D
R
I/O Logic
Address
Latch
Address
Counter
X-Decoder
Y-Decoder
Input Buffer
Output
Buffer
GND
VCC
BYTE#
VPEN
CE0
CE1
CE2
WE#
OE#
RP#
Command
User
Interface
A[MAX:MIN]
D[15:0]
VCC
W
Write State
Machine
Multiplexer
Query
STS
VCCQ
CE
Logic
A[2:0]
相關(guān)PDF資料 |
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| E28F256J3C-120 | Intel StrataFlash Memory (J3) |
| E28F256J3C-125 | Intel StrataFlash Memory (J3) |
| E28F256J3C-150 | Intel StrataFlash Memory (J3) |
| E28F256J3C-110 | Intel StrataFlash Memory (J3) |
| E28F128J3C-110 | Intel StrataFlash Memory (J3) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| E28F256J3C-120 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| E28F256J3C-125 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| E28F256J3C-150 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| E28F320J3A110 | 制造商:Intel 功能描述:Flash Mem Parallel 3V/3.3V 32M-Bit 4M x 8/2M x 16 110ns 56-Pin TSOP Tray 制造商:Intel 功能描述:NOR Flash, 2M x 16, 56 Pin, Plastic, TSSOP |
| E28F320J3A-110 | 制造商:Intel 功能描述:NOR Flash, 2M x 16, 56 Pin, Plastic, TSSOP |
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