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參數(shù)資料
| 型號： | E28F320J3A-115 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel StrataFlash Memory (J3) |
| 中文描述： | 英特爾StrataFlash存儲器（J3） |
| 文件頁數(shù)： | 26/58頁 |
| 文件大?。?/td> | 380K |
| 代理商： | E28F320J3A-115 |
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28F128J3A, 28F640J3A, 28F320J3A
20
Preliminary
NOTES:
1. A
0
is not used in either x8 or x16 modes when obtaining the identifier codes. The lowest order address line is
A
1
. Data is always presented on the low byte in x16 mode (upper byte contains 00h).
2. X selects the specific block
’
s lock configuration code. See
Figure 5
for the device identifier code memory
map.
4.4
Read Status Register Command
The status register may be read to determine when a block erase, program, or lock-bit configuration
is complete and whether the operation completed successfully. It may be read at any time by
writing the Read Status Register command. After writing this command, all subsequent read
operations output data from the status register until another valid command is written. Page-mode
reads are not supported in this read mode. The status register contents are latched on the falling
edge of OE# or the first edge of CE
0
, CE
1
, or CE
2
that enables the device (see
Table 2,
“
Chip
Enable Truth Table
”
on page 7
). OE# must toggle to V
IH
or the device must be disabled (see
Table
2
) before further reads to update the status register latch. The Read Status Register command
functions independently of the V
PEN
voltage.
During a program, block erase, set lock-bit, or clear lock-bit command sequence, only SR.7 is valid
until the Write State Machine completes or suspends the operation. Device I/O pins DQ
0
–
DQ
6
and
DQ
8
–
DQ
15
are placed in a high-impedance state. When the operation completes or suspends
(check status register bit 7), all contents of the status register are valid when read.
Table 15. Identifier Codes
Code
Address
(1)
Data
Manufacture Code
Device Code
00000
00001
00001
00001
X
0002
(2)
(00) 89
(00) 16
(00) 17
(00) 18
32-Mbit
64-Mbit
128-Mbit
Block Lock Configuration
Block Is Unlocked
Block Is Locked
Reserved for Future Use
DQ
0
= 0
DQ
0
= 1
DQ
1
–
7
相關PDF資料 |
PDF描述 |
|---|---|
| E28F320J3A-120 | Intel StrataFlash Memory (J3) |
| E28F320J3A-125 | Intel StrataFlash Memory (J3) |
| E28F320J3A-150 | Intel StrataFlash Memory (J3) |
| E28F320J3C-115 | Intel StrataFlash Memory (J3) |
| E28F320J3C-120 | Intel StrataFlash Memory (J3) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| E28F320J3A-120 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| E28F320J3A-125 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| E28F320J3A-150 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| E28F320J3C-110 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| E28F320J3C-115 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
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